library IEEE; use IEEE.STD_LOGIC_1164.all; package sortnet_tb is generic ( DATA_BITS : positive; INPUTS : positive ); subtype T_DATA is std_logic_vector(DATA_BITS - 1 downto 0); type T_DATA_VECTOR is array(natural range <>) of T_DATA; type T_SCOREBOARD_DATA is record Data : T_DATA_VECTOR(INPUTS - 1 downto 0); end record; end sortnet_tb; entity repro1 is end repro1; architecture behav of repro1 is package tb is new work.sortnet_tb generic map (3, 4); begin end behav; title='iCE40/yosys Git repository'/>
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path: root/tests/asicworld/code_verilog_tutorial_decoder.v
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module decoder (in,out);
input [2:0] in;
output [7:0] out;
wire [7:0] out;
assign out  =  	(in == 3'b000 ) ? 8'b0000_0001 : 
(in == 3'b001 ) ? 8'b0000_0010 : 
(in == 3'b010 ) ? 8'b0000_0100 : 
(in == 3'b011 ) ? 8'b0000_1000 : 
(in == 3'b100 ) ? 8'b0001_0000 : 
(in == 3'b101 ) ? 8'b0010_0000 : 
(in == 3'b110 ) ? 8'b0100_0000 : 
(in == 3'b111 ) ? 8'b1000_0000 : 8'h00;
  	  	 
endmodule
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