library ieee;
use ieee.numeric_std.all;
entity ent is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a of ent is
begin
main : process
variable a,b : unsigned(0 downto 0) := "1";
begin
assert a = b; -- Works
assert ieee.numeric_std."="(a, b);
wait;
end process;
end architecture;
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<a id='n22' href='#n22'>22</a>
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<a id='n24' href='#n24'>24</a>
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</pre></td>
<td class='lines'><pre><code><style>pre { line-height: 125%; margin: 0; }
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.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */</style><div class="highlight"><pre><span></span><span class="cm">/* This is a</span>
<span class="cm"> Multi line comment</span>
<span class="cm"> example */</span>
<span class="k">module</span> <span class="n">addbit</span> <span class="p">(</span>
<span class="n">a</span><span class="p">,</span>
<span class="n">b</span><span class="p">,</span>
<span class="n">ci</span><span class="p">,</span>
<span class="n">sum</span><span class="p">,</span>
<span class="n">co</span><span class="p">);</span>
<span class="c1">// Input Ports Single line comment</span>
<span class="k">input</span> <span class="n">a</span><span class="p">;</span>
<span class="k">input</span> <span class="n">b</span><span class="p">;</span>
<span class="k">input</span> <span class="n">ci</span><span class="p">;</span>
<span class="c1">// Output ports</span>
<span class="k">output</span> <span class="n">sum</span><span class="p">;</span>
<span class="k">output</span> <span class="n">co</span><span class="p">;</span>
<span class="c1">// Data Types </span>
<span class="kt">wire</span> <span class="n">a</span><span class="p">;</span>
<span class="kt">wire</span> <span class="n">b</span><span class="p">;</span>
<span class="kt">wire</span> <span class="n">ci</span><span class="p">;</span>
<span class="kt">wire</span> <span class="n">sum</span><span class="p">;</span>
<span class="kt">wire</span> <span class="n">co</span><span class="p">;</span>
<span class="k">endmodule</span>
</pre></div>
</code></pre></td></tr></table>
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