aboutsummaryrefslogtreecommitdiffstats
path: root/tests/asicworld/code_tidbits_reg_combo_example.v
blob: 9689788c4335fba471251fff5650144fd4199ce0 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
module reg_combo_example( a, b, y);
input a, b;
output y;

reg   y;
wire a, b;

always @ ( a or b)
begin	
  y = a & b;
end

endmodule