aboutsummaryrefslogtreecommitdiffstats
path: root/tests/asicworld/code_tidbits_blocking.v
blob: e13b72cc7d5a30aa98f56362bccf355225a0bd01 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
module blocking (clk,a,c);
input clk;
input a;
output c;
 
wire clk;
wire a;
reg c;
reg b;
  
always @ (posedge clk )
begin
 b = a;
 c = b;
end
   
endmodule