1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
|
module testbench ();
reg clk = 0;
reg rst = 1;
reg req3 = 0;
reg req2 = 0;
reg req1 = 0;
reg req0 = 0;
wire gnt3;
wire gnt2;
wire gnt1;
wire gnt0;
// Clock generator
always #1 clk = ~clk;
integer file;
always @(posedge clk)
$fdisplay(file, "%b", {gnt3, gnt2, gnt1, gnt0});
initial begin
file = $fopen(`outfile);
repeat (5) @ (posedge clk);
rst <= 0;
repeat (1) @ (posedge clk);
req0 <= 1;
repeat (1) @ (posedge clk);
req0 <= 0;
repeat (1) @ (posedge clk);
req0 <= 1;
req1 <= 1;
repeat (1) @ (posedge clk);
req2 <= 1;
req1 <= 0;
repeat (1) @ (posedge clk);
req3 <= 1;
req2 <= 0;
repeat (1) @ (posedge clk);
req3 <= 0;
repeat (1) @ (posedge clk);
req0 <= 0;
repeat (1) @ (posedge clk);
#10 $finish;
end
// Connect the DUT
arbiter U (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
endmodule
|
