1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
|
module mul_plain(a, b, p);
parameter M = 6;
parameter N = 6;
input wire [M-1:0] a;
input wire [N-1:0] b;
output wire [M+N-1:0] p;
assign p = a * b;
endmodule
module mul_signed_async (clk, rst, en, a, b, p);
parameter M = 8;
parameter N = 6;
input wire signed clk, rst, en;
input wire signed [M-1:0] a;
input wire signed [N-1:0] b;
output reg signed [M+N-1:0] p;
reg signed [M-1:0] a_reg;
reg signed [N-1:0] b_reg;
// signed M*N multiplier with
// - input and output pipeline registers
// - asynchronous reset (active high)
// - clock enable (active high)
always @(posedge clk or posedge rst)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule
module mul_unsigned_sync (clk, rst, en, a, b, p);
parameter M = 6;
parameter N = 3;
input wire clk, rst, en;
input wire [M-1:0] a;
input wire [N-1:0] b;
output reg [M+N-1:0] p;
reg [M-1:0] a_reg;
reg [N-1:0] b_reg;
// unsigned M*N multiplier with
// - input and output pipeline registers
// - synchronous reset (active high)
// - clock enable (active high)
always @(posedge clk)
begin
if (rst) begin
a_reg <= 0;
b_reg <= 0;
p <= 0;
end
else if (en) begin
a_reg <= a;
b_reg <= b;
p <= a_reg * b_reg;
end
end
endmodule
|
