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pre { line-height: 125%; margin: 0; }
td.linenos pre { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
span.linenos { color: #000000; background-color: #f0f0f0; padding: 0 5px 0 5px; }
td.linenos pre.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
span.linenos.special { color: #000000; background-color: #ffffc0; padding: 0 5px 0 5px; }
.highlight .hll { background-color: #ffffcc }
.highlight { background: #ffffff; }
.highlight .c { color: #888888 } /* Comment */
.highlight .err { color: #a61717; background-color: #e3d2d2 } /* Error */
.highlight .k { color: #008800; font-weight: bold } /* Keyword */
.highlight .ch { color: #888888 } /* Comment.Hashbang */
.highlight .cm { color: #888888 } /* Comment.Multiline */
.highlight .cp { color: #cc0000; font-weight: bold } /* Comment.Preproc */
.highlight .cpf { color: #888888 } /* Comment.PreprocFile */
.highlight .c1 { color: #888888 } /* Comment.Single */
.highlight .cs { color: #cc0000; font-weight: bold; background-color: #fff0f0 } /* Comment.Special */
.highlight .gd { color: #000000; background-color: #ffdddd } /* Generic.Deleted */
.highlight .ge { font-style: italic } /* Generic.Emph */
.highlight .gr { color: #aa0000 } /* Generic.Error */
.highlight .gh { color: #333333 } /* Generic.Heading */
.highlight .gi { color: #000000; background-color: #ddffdd } /* Generic.Inserted */
.highlight .go { color: #888888 } /* Generic.Output */
.highlight .gp { color: #555555 } /* Generic.Prompt */
.highlight .gs { font-weight: bold } /* Generic.Strong */
.highlight .gu { color: #666666 } /* Generic.Subheading */
.highlight .gt { color: #aa0000 } /* Generic.Traceback */
.highlight .kc { color: #008800; font-weight: bold } /* Keyword.Constant */
.highlight .kd { color: #008800; font-weight: bold } /* Keyword.Declaration */
.highlight .kn { color: #008800; font-weight: bold } /* Keyword.Namespace */
.highlight .kp { color: #008800 } /* Keyword.Pseudo */
.highlight .kr { color: #008800; font-weight: bold } /* Keyword.Reserved */
.highlight .kt { color: #888888; font-weight: bold } /* Keyword.Type */
.highlight .m { color: #0000DD; font-weight: bold } /* Literal.Number */
.highlight .s { color: #dd2200; background-color: #fff0f0 } /* Literal.String */
.highlight .na { color: #336699 } /* Name.Attribute */
.highlight .nb { color: #003388 } /* Name.Builtin */
.highlight .nc { color: #bb0066; font-weight: bold } /* Name.Class */
.highlight .no { color: #003366; font-weight: bold } /* Name.Constant */
.highlight .nd { color: #555555 } /* Name.Decorator */
.highlight .ne { color: #bb0066; font-weight: bold } /* Name.Exception */
.highlight .nf { color: #0066bb; font-weight: bold } /* Name.Function */
.highlight .nl { color: #336699; font-style: italic } /* Name.Label */
.highlight .nn { color: #bb0066; font-weight: bold } /* Name.Namespace */
.highlight .py { color: #336699; font-weight: bold } /* Name.Property */
.highlight .nt { color: #bb0066; font-weight: bold } /* Name.Tag */
.highlight .nv { color: #336699 } /* Name.Variable */
.highlight .ow { color: #008800 } /* Operator.Word */
.highlight .w { color: #bbbbbb } /* Text.Whitespace */
.highlight .mb { color: #0000DD; font-weight: bold } /* Literal.Number.Bin */
.highlight .mf { color: #0000DD; font-weight: bold } /* Literal.Number.Float */
.highlight .mh { color: #0000DD; font-weight: bold } /* Literal.Number.Hex */
.highlight .mi { color: #0000DD; font-weight: bold } /* Literal.Number.Integer */
.highlight .mo { color: #0000DD; font-weight: bold } /* Literal.Number.Oct */
.highlight .sa { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Affix */
.highlight .sb { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Backtick */
.highlight .sc { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Char */
.highlight .dl { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Delimiter */
.highlight .sd { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Doc */
.highlight .s2 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Double */
.highlight .se { color: #0044dd; background-color: #fff0f0 } /* Literal.String.Escape */
.highlight .sh { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Heredoc */
.highlight .si { color: #3333bb; background-color: #fff0f0 } /* Literal.String.Interpol */
.highlight .sx { color: #22bb22; background-color: #f0fff0 } /* Literal.String.Other */
.highlight .sr { color: #008800; background-color: #fff0ff } /* Literal.String.Regex */
.highlight .s1 { color: #dd2200; background-color: #fff0f0 } /* Literal.String.Single */
.highlight .ss { color: #aa6600; background-color: #fff0f0 } /* Literal.String.Symbol */
.highlight .bp { color: #003388 } /* Name.Builtin.Pseudo */
.highlight .fm { color: #0066bb; font-weight: bold } /* Name.Function.Magic */
.highlight .vc { color: #336699 } /* Name.Variable.Class */
.highlight .vg { color: #dd7700 } /* Name.Variable.Global */
.highlight .vi { color: #3333bb } /* Name.Variable.Instance */
.highlight .vm { color: #336699 } /* Name.Variable.Magic */
.highlight .il { color: #0000DD; font-weight: bold } /* Literal.Number.Integer.Long */
#include QMK_KEYBOARD_H

enum layer {
    LAYER_DEFAULT,
    LAYER_LOWER,
    LAYER_RAISE,
    LAYER_ADJUST,
};

#define LY_LWR MO(LAYER_LOWER)
#define LY_RSE MO(LAYER_RAISE)

#define KY_CESC LCTL_T(KC_ESC)

const uint16_t PROGMEM keymaps[][MATRIX_ROWS][MATRIX_COLS] = {
    /* Default layer: http://www.keyboard-layout-editor.com/#/gists/e0eb3af65961e9fd612dcff3ddd88e4f */
    [LAYER_DEFAULT] = LAYOUT(
        KC_EQL,   KC_1,     KC_2,     KC_3,     KC_4,     KC_5,                         KC_6,     KC_7,     KC_8,     KC_9,     KC_0,     KC_MINS,
        KC_TAB,   KC_Q,     KC_W,     KC_E,     KC_R,     KC_T,                         KC_Y,     KC_U,     KC_I,     KC_O,     KC_P,     KC_BSPC,
        KY_CESC,  KC_A,     KC_S,     KC_D,     KC_F,     KC_G,                         KC_H,     KC_J,     KC_K,     KC_L,     KC_SCLN,  KC_QUOT,
        KC_LSFT,  KC_Z,     KC_X,     KC_C,     KC_V,     KC_B,     KC_WBAK,  KC_WFWD,  KC_N,     KC_M,     KC_COMM,  KC_DOT,   KC_SLSH,  KC_RSFT,
                                      KC_LCTL,  KC_LALT,  LY_LWR,   KC_SPC,   KC_ENT,   LY_RSE,   KC_RGUI,  KC_APP
    ),

    /* Lower layer: http://www.keyboard-layout-editor.com/#/gists/19ad0d3b5d745fbb2818db09740f5a11 */
    [LAYER_LOWER] = LAYOUT(
        _______,  _______,  _______,  _______,  _______,  _______,                      _______,  _______,  _______,  _______,  ______
// Ultrascale and Ultrascale Plus block RAM mapping.

module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [36863:0] INIT = 36864'),

    /* Adjust layer: http://www.keyboard-layout-editor.com/#/gists/8f6a3f08350a9bbe1d414b22bca4e6c7 */
    [LAYER_ADJUST] = LAYOUT(
        _______,  _______,  _______,  _______,  _______,  _______,                      _______,  _______,  _______,  _______,  _______,  _______,
        KC_CAPS,  _______,  KC_MPLY,  KC_VOLU,  KC_MSTP,  _______,                      EEP_RST,  RESET,    KC_PSCR,  KC_SLCK,  KC_PAUS,  _______,
        _______,  _______,  KC_MPRV,  KC_VOLD,  KC_MNXT,  _______,        
	wire [7:0] DIP, DOP;
	wire [63:0] DI, DO;

	assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32],
	                  DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1],
n>[ 7: 0] }; assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32], DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; RAMB36E2 #( .READ_WIDTH_A(72), .WRITE_WIDTH_B(72), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .DOA_REG(0), .DOB_REG(0), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_36.vh" ) _TECHMAP_REPLACE_ ( .DOUTBDOUT(DO[63:32]), .DOUTADOUT(DO[31:0]), .DOUTPBDOUTP(DOP[7:4]), .DOUTPADOUTP(DOP[3:0]), .DINBDIN(DI[63:32]), .DINADIN(DI[31:0]), .DINPBDINP(DIP[7:4]), .DINPADINP(DIP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .ADDRENA(|1), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(4'b0), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), .ADDRENB(|1), .REGCEB(|1), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN), .SLEEP(|0) ); endmodule // ------------------------------------------------------------------------ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [18431:0] INIT = 18432'bx; input CLK2; input CLK3; input [8:0] A1ADDR; output [35:0] A1DATA; input A1EN; input [8:0] B1ADDR; input [35:0] B1DATA; input [3:0] B1EN; wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0}; wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0}; wire [3:0] DIP, DOP; wire [31:0] DI, DO; assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; RAMB18E2 #( .READ_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .DOA_REG(0), .DOB_REG(0), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_18.vh" ) _TECHMAP_REPLACE_ ( .DOUTBDOUT(DO[31:16]), .DOUTADOUT(DO[15:0]), .DOUTPBDOUTP(DOP[3:2]), .DOUTPADOUTP(DOP[1:0]), .DINBDIN(DI[31:16]), .DINADIN(DI[15:0]), .DINPBDINP(DIP[3:2]), .DINPADINP(DIP[1:0]), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .ADDRENA(|1), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(2'b0), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), .ADDRENB(|1), .REGCEB(|1), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN), .SLEEP(|0) ); endmodule // ------------------------------------------------------------------------ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 36; parameter CFG_ENABLE_B = 4; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [36863:0] INIT = 36864'bx; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS); wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS); wire [7:0] B1EN_8 = B1EN; wire [3:0] DIP, DOP; wire [31:0] DI, DO; wire [31:0] DOBDO; wire [3:0] DOPBDOP; assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; generate if (CFG_DBITS > 8) begin RAMB36E2 #( .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .DOA_REG(0), .DOB_REG(0), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_36.vh" ) _TECHMAP_REPLACE_ ( .DINADIN(32'hFFFFFFFF), .DINPADINP(4'hF), .DOUTADOUT(DO[31:0]), .DOUTPADOUTP(DOP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .ADDRENA(|1), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(4'b0), .DINBDIN(DI), .DINPBDINP(DIP), .DOUTBDOUT(DOBDO), .DOUTPBDOUTP(DOPBDOP), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), .ADDRENB(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_8), .SLEEP(|0) ); end else begin RAMB36E2 #( .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .DOA_REG(0), .DOB_REG(0), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_32.vh" ) _TECHMAP_REPLACE_ ( .DINADIN(32'hFFFFFFFF), .DINPADINP(4'hF), .DOUTADOUT(DO[31:0]), .DOUTPADOUTP(DOP[3:0]), .ADDRARDADDR(A1ADDR_16), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .ADDRENA(|1), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(4'b0), .DINBDIN(DI), .DINPBDINP(DIP), .DOUTBDOUT(DOBDO), .DOUTPBDOUTP(DOPBDOP), .ADDRBWRADDR(B1ADDR_16), .CLKBWRCLK(CLK3), .ENBWREN(|1), .ADDRENB(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_8), .SLEEP(|0) ); end endgenerate endmodule // ------------------------------------------------------------------------ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 18; parameter CFG_ENABLE_B = 2; parameter CLKPOL2 = 1; parameter CLKPOL3 = 1; parameter [18431:0] INIT = 18432'bx; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; output [CFG_DBITS-1:0] A1DATA; input A1EN; input [CFG_ABITS-1:0] B1ADDR; input [CFG_DBITS-1:0] B1DATA; input [CFG_ENABLE_B-1:0] B1EN; wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS); wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS); wire [3:0] B1EN_4 = B1EN; wire [1:0] DIP, DOP; wire [15:0] DI, DO; wire [15:0] DOBDO; wire [1:0] DOPBDOP; assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; generate if (CFG_DBITS > 8) begin RAMB18E2 #( .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .DOA_REG(0), .DOB_REG(0), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_18.vh" ) _TECHMAP_REPLACE_ ( .DINADIN(16'hFFFF), .DINPADINP(2'b11), .DOUTADOUT(DO), .DOUTPADOUTP(DOP), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .ADDRENA(|1), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(2'b0), .DINBDIN(DI), .DINPBDINP(DIP), .DOUTBDOUT(DOBDO), .DOUTPBDOUTP(DOPBDOP), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), .ADDRENB(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_4), .SLEEP(|0) ); end else begin RAMB18E2 #( //.RAM_MODE("TDP"), .READ_WIDTH_A(CFG_DBITS), .READ_WIDTH_B(CFG_DBITS), .WRITE_WIDTH_A(CFG_DBITS), .WRITE_WIDTH_B(CFG_DBITS), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .DOA_REG(0), .DOB_REG(0), .IS_CLKARDCLK_INVERTED(!CLKPOL2), .IS_CLKBWRCLK_INVERTED(!CLKPOL3), `include "brams_init_16.vh" ) _TECHMAP_REPLACE_ ( .DINADIN(16'hFFFF), .DINPADINP(2'b11), .DOUTADOUT(DO), .DOUTPADOUTP(DOP), .ADDRARDADDR(A1ADDR_14), .CLKARDCLK(CLK2), .ENARDEN(A1EN), .ADDRENA(|1), .REGCEAREGCE(|1), .RSTRAMARSTRAM(|0), .RSTREGARSTREG(|0), .WEA(2'b0), .DINBDIN(DI), .DINPBDINP(DIP), .DOUTBDOUT(DOBDO), .DOUTPBDOUTP(DOPBDOP), .ADDRBWRADDR(B1ADDR_14), .CLKBWRCLK(CLK3), .ENBWREN(|1), .ADDRENB(|1), .REGCEB(|0), .RSTRAMB(|0), .RSTREGB(|0), .WEBWE(B1EN_4), .SLEEP(|0) ); end endgenerate endmodule