bram2.sh « tests « xilinx « techlibs - iCE40/yosys - clone of https://github.com/YosysHQ/yosys

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path: root/techlibs/xilinx/tests/bram2.sh

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#!/bin/bash

set -ex
unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
../../../yosys -v2 -l bram2.log -p synth_xilinx -o bram2_syn.v bram2.v
iverilog -T typ -o bram2_tb bram2_tb.v bram2_syn.v -y $unisims $unisims/../glbl.v
vvp -N bram2_tb

an> ieee.std_logic_1164.all; entity subs is port ( li : integer; ri : integer; l4 : std_logic_vector (3 downto 0); r3 : std_logic_vector (2 downto 0); sub_v4v3 : out std_logic_vector (3 downto 0); sub_v4i : out std_logic_vector (3 downto 0); sub_iv3 : out std_logic_vector (2 downto 0); sub_v4l : out std_logic_vector (3 downto 0); sub_lv3 : out std_logic_vector (2 downto 0)); end subs; library ieee; use ieee.std_logic_signed.all; architecture behav of subs is begin sub_v4v3 <= l4 - r3; sub_v4i <= l4 - ri; sub_iv3 <= li - r3; sub_v4l <= l4 - r3(0); sub_lv3 <= l4(0) - r3; end behav;