aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/xilinx/drams_bb.v
blob: 11168fe131a234d80d6727d6cd980701e2d600e2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
module RAM64X1D (
	output DPO, SPO,
	input  D, WCLK, WE,
	input  A0, A1, A2, A3, A4, A5,
	input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
);
	parameter INIT = 64'h0;
	parameter IS_WCLK_INVERTED = 1'b0;
endmodule

module RAM128X1D (
	output       DPO, SPO,
	input        D, WCLK, WE,
	input  [6:0] A, DPRA
);
	parameter INIT = 128'h0;
	parameter IS_WCLK_INVERTED = 1'b0;
endmodule