blob: 69214fd596a2787338c2667529f4fca37e56e124 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
|
bram $__XILINX_RAMB36_SDP72
abits 9
dbits 72
groups 2
ports 1 1
wrmode 0 1
enable 0 8
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_SDP36
abits 10
dbits 36
groups 2
ports 1 1
wrmode 0 1
enable 0 4
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_SDP18
abits 11
dbits 18
groups 2
ports 1 1
wrmode 0 1
enable 0 2
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_SDP9
abits 12
dbits 9
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_SDP4
abits 13
dbits 4
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_SDP2
abits 14
dbits 2
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
bram $__XILINX_RAMB36_SDP1
abits 15
dbits 1
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 2 0
clocks 2 3
clkpol 2 3
endbram
match $__XILINX_RAMB36_SDP72
shuffle_enable 8
# min efficiency 20
# or_next_if_better
endmatch
# match $__XILINX_RAMB36_SDP36
# shuffle_enable 4
# min efficiency 20
# or_next_if_better
# endmatch
#
# match $__XILINX_RAMB36_SDP18
# shuffle_enable 2
# min efficiency 20
# or_next_if_better
# endmatch
#
# match $__XILINX_RAMB36_SDP9
# min efficiency 20
# or_next_if_better
# endmatch
#
# match $__XILINX_RAMB36_SDP4
# min efficiency 20
# or_next_if_better
# endmatch
#
# match $__XILINX_RAMB36_SDP2
# min efficiency 20
# or_next_if_better
# endmatch
#
# match $__XILINX_RAMB36_SDP1
# min efficiency 20
# endmatch
|