techlibs/intel_alm/common/lutram_mlab.txt


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

bram MISTRAL_MLAB
    init   0   # TODO: Re-enable when Yosys remembers the original filename.
    abits  5
    dbits  1
    groups 2
    ports  1 1
    wrmode 1 0
    # write enable
    enable 1 0
    transp 0 0
    clocks 1 0
    clkpol 1 1
endbram

match MISTRAL_MLAB
    min efficiency 5
    make_outreg
endmatch