techlibs/intel/common/brams_map.v


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95

module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);

   parameter CFG_ABITS = 8;
   parameter CFG_DBITS = 36;
   parameter ABITS = "1"; 
   parameter DBITS = "1"; 
   parameter CLKPOL2 = 1;
   parameter CLKPOL3 = 1;
   
   input CLK2;
   input CLK3;
   //Read data
   output [CFG_DBITS-1:0] A1DATA;
   input [CFG_ABITS-1:0]  A1ADDR;
   input                  A1EN;
   //Write data
   output [CFG_DBITS-1:0] B1DATA;
   input [CFG_ABITS-1:0]  B1ADDR;
   input                  B1EN;

   wire [CFG_DBITS-1:0]   B1DATA_t;
   
   localparam MODE = CFG_DBITS == 1  ? 1:
                     CFG_DBITS == 2  ? 2:
                     CFG_DBITS == 4  ? 3:
                     CFG_DBITS == 8  ? 4:
                     CFG_DBITS == 9  ? 5:
                     CFG_DBITS == 16 ? 6:
                     CFG_DBITS == 18 ? 7:
                     CFG_DBITS == 32 ? 8:
                     CFG_DBITS == 36 ? 9:
                     'bx;
   
   localparam NUMWORDS = CFG_DBITS == 1  ? "8192":
                         CFG_DBITS == 2  ? "4096":
                         CFG_DBITS == 4  ? "2048":
                         CFG_DBITS == 8  ? "1024":
                         CFG_DBITS == 9  ? "1024":
                         CFG_DBITS == 16 ?  "512":
                         CFG_DBITS == 18 ?  "512":
                         CFG_DBITS == 32 ?  "256":
                         CFG_DBITS == 36 ?  "256":
                         'bx;
   /* Killing some stupid warnings and assignations*/
  /* generate
      if( MODE == 1 ) begin
         assign B1DATA_t = ({34{1'b0},B1DATA[0]});
      end
   endgenerate*/
   
   altsyncram  #(.clock_enable_input_b   ("ALTERNATE"   ), 
                 .clock_enable_input_a   ("ALTERNATE"   ), 
                 .clock_enable_output_b  ("NORMAL"      ), 
                 .clock_enable_output_a  ("NORMAL"      ), 
                 .wrcontrol_aclr_a       ("NONE"        ), 
                 .indata_aclr_a          ("NONE"        ), 
                 .address_aclr_a         ("NONE"        ), 
                 .outdata_aclr_a         ("NONE"        ), 
                 .outdata_reg_a          ("UNREGISTERED"), 
                 .operation_mode         ("SINGLE_PORT" ), 
                 .intended_device_family ("CYCLONE IVE" ), 
                 .outdata_reg_a          ("UNREGISTERED"), 
                 .lpm_type               ("altsyncram"  ), 
                 .init_type              ("unused"      ), 
                 .ram_block_type         ("AUTO"        ), 
                 .numwords_b             ( NUMWORDS     ), 
                 .numwords_a             ( NUMWORDS     ), 
                 .widthad_b              ( CFG_ABITS    ), 
                 .width_b                ( CFG_DBITS    ),     
                 .widthad_a              ( CFG_ABITS    ), 
                 .width_a                ( CFG_DBITS    ) 
                 ) _TECHMAP_REPLACE_ (
                                      .data_a(B1DATA),
                                      .address_a(B1ADDR),
                                      .wren_a(B1EN),
                                      .rden_a(A1EN),
                                      .q_a(A1DATA),
                                      .data_b(1'b0),
                                      .address_b(0),
                                      .wren_b(1'b0),
                                      .rden_b(1'b0),
                                      .q_b(1'b0),
                                      .clock0(CLK2), 
                                      .clock1(1'b1), // Unused in single port mode
                                      .clocken0(1'b1),
                                      .clocken1(1'b1),
                                      .clocken2(1'b1),
                                      .clocken3(1'b1),
                                      .aclr0(1'b0), 
                                      .aclr1(1'b0),
                                      .addressstall_a(1'b0),
                                      .addressstall_b(1'b0));
   
endmodule