AIGER is a format for And-Inverter Graphs (AIGs). See http://fmv.jku.at/aiger/ for details. AIGER is used in the Hardware Model Checking Competition (HWMCC), therefore all solvers competing in the competition have to support the format. The example in this directory is using super_prove as solver. Check http://downloads.bvsrc.org/super_prove/ for the lates release. (See https://bitbucket.org/sterin/super_prove_build for sources.) The "demo.sh" script in this directory expects a "super_prove" executable in the PATH. E.g. extract the release to /usr/local/libexec/super_prove and then create a /usr/local/bin/super_prove file with the following contents (and "chmod +x" that file): #!/bin/bash exec /usr/local/libexec/super_prove/bin/super_prove.sh "$@" The "demo.sh" script also expects the "z3" SMT2 solver in the PATH for converting the witness file generated by super_prove to VCD using yosys-smtbmc. See https://github.com/Z3Prover/z3 for install notes. '> clone of https://github.com/YosysHQ/yosys
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path: root/techlibs/intel/Makefile.inc
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OBJS += techlibs/intel/synth_intel.o

$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))

# Add the cell models and mappings for the VQM backend
families := max10 cyclone10lp cycloneiv cycloneive
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))