blob: af834b005fd544b9a985389e7c8ef3ae0787aba8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
# Yosys doesn't support configurable sync/async ports.
# So we define three RAMs for 2xasync, 1xsync 1xasync and 2xsync
ram distributed $__REGFILE_AA_ {
abits 5;
width 4;
cost 6;
port sw "W" {
clock posedge "CLK";
}
port ar "A" {
}
port ar "B" {
}
}
ram distributed $__REGFILE_SA_ {
abits 5;
width 4;
cost 5;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port ar "B" {
}
}
ram distributed $__REGFILE_SS_ {
abits 5;
width 4;
cost 4;
port sw "W" {
clock posedge "CLK";
wrtrans all old;
}
port sr "A" {
clock posedge "CLK";
}
port sr "B" {
clock posedge "CLK";
}
}
|
