/* * nextpnr -- Next Generation Place and Route * * Copyright (C) 2018 Clifford Wolf * Copyright (C) 2018 David Shah * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ #ifndef PCF_H #define PCF_H #include #include "nextpnr.h" NEXTPNR_NAMESPACE_BEGIN // Apply PCF constraints to a pre-packing design bool apply_pcf(Context *ctx, std::string filename, std::istream &in); NEXTPNR_NAMESPACE_END #endif // ROUTE_H aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs/efinix/brams_map.v
blob: 6786ae76970bc886db9b68328b0615831f39b16c (plain) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65

module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
	parameter CFG_ABITS = 8;
	parameter CFG_DBITS = 20;
	parameter CFG_ENABLE_A = 1;

	parameter CLKPOL2 = 1;
	parameter CLKPOL3 = 1;
	parameter [5119:0] INIT = 5119'bx;
	parameter TRANSP2 = 0;

	input CLK2;
	input CLK3;

	input [CFG_ABITS-1:0] A1ADDR;
	input [CFG_DBITS-1:0] A1DATA;
	input [CFG_ENABLE_A-1:0] A1EN;

	input [CFG_ABITS-1:0] B1ADDR;
	output [CFG_DBITS-1:0] B1DATA;
	input B1EN;

	localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";

	EFX_RAM_5K #(
   		.READ_WIDTH(CFG_DBITS),
   		.WRITE_WIDTH(CFG_DBITS),
   		.OUTPUT_REG(1'b0),
   		.RCLK_POLARITY(1'b1),
   		.RE_POLARITY(1'b1),
   		.WCLK_POLARITY(1'b1),
   		.WE_POLARITY(1'b1),
   		.WCLKE_POLARITY(1'b1),
   		.WRITE_MODE(WRITEMODE_A),
		.INIT_0(INIT[ 0*256 +: 256]),
		.INIT_1(INIT[ 1*256 +: 256]),
		.INIT_2(INIT[ 2*256 +: 256]),
		.INIT_3(INIT[ 3*256 +: 256]),
		.INIT_4(INIT[ 4*256 +: 256]),
		.INIT_5(INIT[ 5*256 +: 256]),
		.INIT_6(INIT[ 6*256 +: 256]),
		.INIT_7(INIT[ 7*256 +: 256]),
		.INIT_8(INIT[ 8*256 +: 256]),
		.INIT_9(INIT[ 9*256 +: 256]),
		.INIT_A(INIT[10*256 +: 256]),
		.INIT_B(INIT[11*256 +: 256]),
		.INIT_C(INIT[12*256 +: 256]),
		.INIT_D(INIT[13*256 +: 256]),
		.INIT_E(INIT[14*256 +: 256]),
		.INIT_F(INIT[15*256 +: 256]),
		.INIT_10(INIT[16*256 +: 256]),
		.INIT_11(INIT[17*256 +: 256]),
		.INIT_12(INIT[18*256 +: 256]),
		.INIT_13(INIT[19*256 +: 256])
	) _TECHMAP_REPLACE_ (
   		.WDATA(A1DATA),
   		.WADDR(A1ADDR),
   		.WE(A1EN),
   		.WCLK(CLK2),
   		.WCLKE(1'b1),
   		.RDATA(B1DATA),
   		.RADDR(B1ADDR),
   		.RE(B1EN),
   		.RCLK(CLK3)
	);
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2025-05-28 01:52:29 +0000