1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct NlutmapConfig
{
vector<int> luts;
};
struct NlutmapWorker
{
const NlutmapConfig &config;
pool<Cell*> mapped_cells;
Module *module;
NlutmapWorker(const NlutmapConfig &config, Module *module) :
config(config), module(module)
{
}
RTLIL::Selection get_selection()
{
RTLIL::Selection sel(false);
for (auto cell : module->cells())
if (!mapped_cells.count(cell))
sel.select(module, cell);
return sel;
}
void run_abc(int lut_size)
{
Pass::call_on_selection(module->design, get_selection(), "lut2mux");
if (lut_size > 0)
Pass::call_on_selection(module->design, get_selection(), stringf("abc -lut 1:%d", lut_size));
else
Pass::call_on_selection(module->design, get_selection(), "abc");
Pass::call_on_module(module->design, module, "opt_clean");
}
void run()
{
vector<int> available_luts = config.luts;
while (GetSize(available_luts) > 1)
{
int n_luts = available_luts.back();
int lut_size = GetSize(available_luts);
available_luts.pop_back();
if (n_luts == 0)
continue;
run_abc(lut_size);
SigMap sigmap(module);
dict<Cell*, int> candidate_ratings;
dict<SigBit, int> bit_lut_count;
for (auto cell : module->cells())
{
if (cell->type != "$lut" || mapped_cells.count(cell))
continue;
if (GetSize(cell->getPort("\\A")) == lut_size || lut_size == 2)
candidate_ratings[cell] = 0;
for (auto &conn : cell->connections())
for (auto bit : sigmap(conn.second))
bit_lut_count[bit]++;
}
for (auto &cand : candidate_ratings)
{
for (auto &conn : cand.first->connections())
for (auto bit : sigmap(conn.second))
cand.second -= bit_lut_count[bit];
}
vector<pair<int, IdString>> rated_candidates;
for (auto &cand : candidate_ratings)
rated_candidates.push_back(pair<int, IdString>(cand.second, cand.first->name));
std::sort(rated_candidates.begin(), rated_candidates.end());
while (n_luts > 0 && !rated_candidates.empty()) {
mapped_cells.insert(module->cell(rated_candidates.back().second));
rated_candidates.pop_back();
n_luts--;
}
if (!available_luts.empty())
available_luts.back() += n_luts;
}
run_abc(0);
}
};
struct NlutmapPass : public Pass {
NlutmapPass() : Pass("nlutmap", "map to LUTs of different sizes") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" nlutmap [options] [selection]\n");
log("\n");
log("This pass uses successive calls to 'abc' to map to an architecture. That\n");
log("provides a small number of differently sized LUTs.\n");
log("\n");
log(" -luts N_1,N_2,N_3,...\n");
log(" The number of LUTs with 1, 2, 3, ... inputs that are\n");
log(" available in the target architecture.\n");
log("\n");
log("Excess logic that does not fit into the specified LUTs is mapped back\n");
log("to generic logic gates ($_AND_, etc.).\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
NlutmapConfig config;
log_header("Executing NLUTMAP pass (mapping to constant drivers).\n");
log_push();
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-luts" && argidx+1 < args.size()) {
vector<string> tokens = split_tokens(args[++argidx], ",");
config.luts.clear();
for (auto &token : tokens)
config.luts.push_back(atoi(token.c_str()));
continue;
}
break;
}
extra_args(args, argidx, design);
for (auto module : design->selected_whole_modules_warn())
{
NlutmapWorker worker(config, module);
worker.run();
}
log_pop();
}
} NlutmapPass;
PRIVATE_NAMESPACE_END
|