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/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#ifndef LIBPARSE_H
#define LIBPARSE_H

#include <stdio.h>
#include <string>
#include <vector>
#include <set>

namespace Yosys
{
	struct LibertyAst
	{
		std::string id, value;
		std::vector<std::string> args;
		std::vector<LibertyAst*> children;
		~LibertyAst();
		LibertyAst *find(std::string name);
		void dump(FILE *f, std::string indent = "", std::string path = "", bool path_ok = false);
		static std::set<std::string> blacklist;
		static std::set<std::string> whitelist;
	};

	struct LibertyParser
	{
		std::istream &f;
		int line;
		LibertyAst *ast;
		LibertyParser(std::istream &f) : f(f), line(1), ast(parse()) {}
		~LibertyParser() { if (ast) delete ast; }
		int lexer(std::string &str);
		LibertyAst *parse();
		void error();
	};
}

#endif
s="k">\def\C#1{\lstinline[language=C++]{#1}} \def\V#1{\lstinline[language=Verilog]{#1}} \lstdefinelanguage{liberty}{ morecomment=[s]{/*}{*/}, morekeywords={library,cell,area,pin,direction,function,clocked_on,next_state,clock,ff}, morestring=[b]", } \lstdefinelanguage{rtlil}{ morecomment=[l]{\#}, morekeywords={module,attribute,parameter,wire,memory,auto,width,offset,size,input,output,inout,cell,connect,switch,case,assign,sync,low,high,posedge,negedge,edge,always,update,process,end}, morestring=[b]", } \lstdefinelanguage{ys}{ morecomment=[l]{\#}, } \lstset{ commentstyle=\color{YosysGreen}, } \newenvironment{boxalertenv}{\begin{altenv}% {\usebeamertemplate{alerted text begin}\usebeamercolor[fg]{alerted text}\usebeamerfont{alerted text}\setlength{\fboxsep}{1pt}\colorbox{bg}} {\usebeamertemplate{alerted text end}}{\color{.}}{}}{\end{altenv}} \newcommand<>{\boxalert}[1]{{% \begin{boxalertenv}#2{#1}\end{boxalertenv}% }} \newcommand{\subsectionpagesuffix}{ \vfill\begin{centering} {\usebeamerfont{subsection name}\usebeamercolor[fg]{subsection name}of \sectionname~\insertsectionnumber} \vskip1em\par \setbeamercolor{graybox}{bg=gray} \begin{beamercolorbox}[sep=8pt,center]{graybox} \usebeamerfont{subsection title}\insertsection\par \end{beamercolorbox} \end{centering}} \title{Yosys Open SYnthesis Suite} \author{Clifford Wolf} \institute{http://www.clifford.at/yosys/} \usetheme{Madrid} \usecolortheme{seagull} \beamertemplatenavigationsymbolsempty \definecolor{YosysGreen}{RGB}{85,136,102} \definecolor{MyBlue}{RGB}{85,130,180} \setbeamercolor{title}{fg=black,bg=YosysGreen!70} \setbeamercolor{titlelike}{fg=black,bg=YosysGreen!70} \setbeamercolor{frametitle}{fg=black,bg=YosysGreen!70} \setbeamercolor{block title}{fg=black,bg=YosysGreen!70} \setbeamercolor{item projected}{fg=black,bg=YosysGreen} \begin{document} \begin{frame} \titlepage \end{frame} \setcounter{section}{-3} \section{Abstract} \begin{frame}{Abstract} Yosys is the first full-featured open source software for Verilog HDL synthesis. It supports most of Verilog-2005 and is well tested with real-world designs from the ASIC and FPGA world. \bigskip Learn how to use Yosys to create your own custom synthesis flows and discover why open source HDL synthesis is important for researchers, hobbyists, educators and engineers alike. \bigskip This presentation covers basic concepts of Yosys, writing synthesis scripts for a wide range of applications, creating Yosys scripts for various non-synthesis applications (such as formal equivalence checking) and writing extensions to Yosys using the C++ API. \end{frame} \section{About me} \begin{frame}{About me} Hi! I'm Clifford Wolf. \bigskip I like writing open source software. For example: \begin{itemize} \item Yosys \item OpenSCAD (now maintained by Marius Kintel) \item SPL (a not very popular scripting language) \item EmbedVM (a very simple compiler+vm for 8 bit micros) \item Lib(X)SVF (a library to play SVF/XSVF files over JTAG) \item ROCK Linux (discontinued since 2010) \end{itemize} \end{frame} \section{Outline} \begin{frame}{Outline} Yosys is an Open Source Verilog synthesis tool, and more. \bigskip Outline of this presentation: \begin{itemize} \item Introduction to the field and Yosys \item Yosys by example: synthesis \item Yosys by example: advanced synthesis \item Yosys by example: beyond synthesis \item Writing Yosys extensions in C++ \end{itemize} \end{frame} \include{PRESENTATION_Intro} \include{PRESENTATION_ExSyn} \include{PRESENTATION_ExAdv} \include{PRESENTATION_ExOth} \include{PRESENTATION_Prog} \end{document}