aboutsummaryrefslogtreecommitdiffstats
path: root/passes/techmap/dff2dffs.cc
blob: 6c2cca4bc5c4e75df02eaa4464e6f46d48e42fb6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
 *  Copyright (C) 2018  David Shah <dave@ds0.me>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/yosys.h"
#include "kernel/sigtools.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct Dff2dffsPass : public Pass {
	Dff2dffsPass() : Pass("dff2dffs", "process sync set/reset with SR over CE priority") { }
	void help() override
	{
		log("\n");
		log("    dff2dffs [options] [selection]\n");
		log("\n");
		log("Merge synchronous set/reset $_MUX_ cells to create $_SDFF_[NP][NP][01]_, to be run before\n");
		log("dff2dffe for SR over CE priority.\n");
		log("\n");
		log("    -match-init\n");
		log("        Disallow merging synchronous set/reset that has polarity opposite of the\n");
		log("        output wire's init attribute (if any).\n");
		log("\n");
	}
	void execute(std::vector<std::string> args, RTLIL::Design *design) override
	{
		log_header(design, "Executing dff2dffs pass (merge synchronous set/reset into FF cells).\n");

		bool match_init = false;
		size_t argidx;
		for (argidx = 1; argidx < args.size(); argidx++)
		{
			// if (args[argidx] == "-singleton") {
			// 	singleton_mode = true;
			// 	continue;
			// }
			if (args[argidx] == "-match-init") {
				match_init = true;
				continue;
			}
			break;
		}
		extra_args(args, argidx, design);

		pool<IdString> dff_types;
		dff_types.insert(ID($_DFF_N_));
		dff_types.insert(ID($_DFF_P_));

		for (auto module : design->selected_modules())
		{
			log("Merging set/reset $_MUX_ cells into DFFs in %s.\n", log_id(module));

			SigMap sigmap(module);
			dict<SigBit, Cell*> sr_muxes;
			vector<Cell*> ff_cells;

			for (auto cell : module->selected_cells())
			{
				if (dff_types.count(cell->type)) {
					ff_cells.push_back(cell);
					continue;
				}

				if (cell->type != ID($_MUX_))
					continue;

				SigBit bit_a = sigmap(cell->getPort(ID::A));
				SigBit bit_b = sigmap(cell->getPort(ID::B));

				if (bit_a.wire == nullptr || bit_b.wire == nullptr)
					sr_muxes[sigmap(cell->getPort(ID::Y))] = cell;
			}

			for (auto cell : ff_cells)
			{
				SigSpec sig_d = cell->getPort(ID::D);

				if (GetSize(sig_d) < 1)
					continue;

				SigBit bit_d = sigmap(sig_d[0]);

				if (sr_muxes.count(bit_d) == 0)
					continue;

				Cell *mux_cell = sr_muxes.at(bit_d);
				SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
				SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
				SigBit bit_s = sigmap(mux_cell->getPort(ID::S));

				SigBit sr_val, sr_sig;
				bool invert_sr;
				sr_sig = bit_s;
				if (bit_a.wire == nullptr) {
					bit_d = bit_b;
					sr_val = bit_a;
					invert_sr = true;
				} else {
					log_assert(bit_b.wire == nullptr);
					bit_d = bit_a;
					sr_val = bit_b;
					invert_sr = false;
				}

				if (match_init) {
					SigBit bit_q = cell->getPort(ID::Q);
					if (bit_q.wire) {
						auto it = bit_q.wire->attributes.find(ID::init);
						if (it != bit_q.wire->attributes.end()) {
							auto init_val = it->second[bit_q.offset];
							if (init_val == State::S1 && sr_val != State::S1)
								continue;
							if (init_val == State::S0 && sr_val != State::S0)
								continue;
						}
					}
				}

				log("  Merging %s (A=%s, B=%s, S=%s) into %s (%s).\n", log_id(mux_cell),
						log_signal(bit_a), log_signal(bit_b), log_signal(bit_s), log_id(cell), log_id(cell->type));

				if (sr_val == State::S1) {
					if (cell->type == ID($_DFF_N_)) {
						if (invert_sr) cell->type = ID($_SDFF_NN1_);
						else cell->type = ID($_SDFF_NP1_);
					} else {
						log_assert(cell->type == ID($_DFF_P_));
						if (invert_sr) cell->type = ID($_SDFF_PN1_);
						else cell->type = ID($_SDFF_PP1_);
					}
				} else {
					if (cell->type == ID($_DFF_N_)) {
						if (invert_sr) cell->type = ID($_SDFF_NN0_);
						else cell->type = ID($_SDFF_NP0_);
					} else {
						log_assert(cell->type == ID($_DFF_P_));
						if (invert_sr) cell->type = ID($_SDFF_PN0_);
						else cell->type = ID($_SDFF_PP0_);
					}
				}
				cell->setPort(ID::R, sr_sig);
				cell->setPort(ID::D, bit_d);
			}
		}
	}
} Dff2dffsPass;

PRIVATE_NAMESPACE_END