aboutsummaryrefslogtreecommitdiffstats
path: root/passes/techmap/bmuxmap.cc
blob: 03673c2787833d270edcabcfd4e25ba54d459746 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
/*
 *  yosys -- Yosys Open SYnthesis Suite
 *
 *  Copyright (C) 2022  Marcelina Kościelnicka <mwk@0x04.net>
 *
 *  Permission to use, copy, modify, and/or distribute this software for any
 *  purpose with or without fee is hereby granted, provided that the above
 *  copyright notice and this permission notice appear in all copies.
 *
 *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 *
 */

#include "kernel/yosys.h"
#include "kernel/sigtools.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct BmuxmapPass : public Pass {
	BmuxmapPass() : Pass("bmuxmap", "transform $bmux cells to trees of $mux cells") { }
	void help() override
	{
		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
		log("\n");
		log("    bmuxmap [selection]\n");
		log("\n");
		log("This pass transforms $bmux cells to trees of $mux cells.\n");
		log("\n");
	}
	void execute(std::vector<std::string> args, RTLIL::Design *design) override
	{
		log_header(design, "Executing BMUXMAP pass.\n");

		size_t argidx;
		for (argidx = 1; argidx < args.size(); argidx++) {
			break;
		}
		extra_args(args, argidx, design);

		for (auto module : design->selected_modules())
		for (auto cell : module->selected_cells())
		{
			if (cell->type != ID($bmux))
				continue;

			SigSpec sel = cell->getPort(ID::S);
			SigSpec data = cell->getPort(ID::A);
			int width = GetSize(cell->getPort(ID::Y));

			for (int idx = 0; idx < GetSize(sel); idx++) {
				SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
				for (int i = 0; i < GetSize(new_data); i += width) {
					RTLIL::Cell *mux = module->addMux(NEW_ID,
							data.extract(i*2, width),
							data.extract(i*2+width, width),
							sel[idx],
							new_data.extract(i, width));
					mux->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
				}
				data = new_data;
			}

			module->connect(cell->getPort(ID::Y), data);
			module->remove(cell);
		}
	}
} BmuxmapPass;

PRIVATE_NAMESPACE_END