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Name
Size
-rw-r--r--
.gitignore
71
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APPNOTE_010_Verilog_to_BLIF.tex
16959
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APPNOTE_011_Design_Investigation.tex
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APPNOTE_011_Design_Investigation
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CHAPTER_Appnotes.tex
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CHAPTER_Approach.tex
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CHAPTER_Auxlibs.tex
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CHAPTER_Auxprogs.tex
816
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CHAPTER_Basics.tex
37570
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CHAPTER_CellLib.tex
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CHAPTER_Eval.tex
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CHAPTER_Eval
281
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CHAPTER_Intro.tex
5057
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CHAPTER_Optimize.tex
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CHAPTER_Overview.tex
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CHAPTER_Prog.tex
1123
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CHAPTER_Prog
147
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CHAPTER_StateOfTheArt.tex
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CHAPTER_StateOfTheArt
725
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CHAPTER_Techmap.tex
5228
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CHAPTER_Verilog.tex
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PRESENTATION_ExAdv.tex
33866
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PRESENTATION_ExAdv
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PRESENTATION_ExOth.tex
6929
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PRESENTATION_ExOth
309
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PRESENTATION_ExSyn.tex
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PRESENTATION_ExSyn
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PRESENTATION_Intro.tex
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PRESENTATION_Intro
225
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PRESENTATION_Prog.tex
21069
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PRESENTATION_Prog
192
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appnotes.sh
450
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clean.sh
143
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command-reference-manual.tex
89794
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literature.bib
6600
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manual.sh
818
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manual.tex
6829
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presentation.sh
808
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presentation.tex
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weblinks.bib
3804
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