1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
|
@misc{YosysGit,
author = {Claire Xenia Wolf},
title = {{Yosys Open SYnthesis Suite (YOSYS)}},
note = {\url{http://github.com/YosysHQ/yosys}}
}
@misc{YosysTestsGit,
author = {Claire Xenia Wolf},
title = {{Yosys Test Bench}},
note = {\url{http://github.com/YosysHQ/yosys-tests}}
}
@misc{VlogHammer,
author = {Claire Xenia Wolf},
title = {{VlogHammer Verilog Synthesis Regression Tests}},
note = {\url{http://github.com/YosysHQ/VlogHammer}}
}
@misc{Icarus,
author = {Stephen Williams},
title = {{Icarus Verilog}},
note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}
}
@misc{VTR,
author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},
note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
}
@misc{HANA,
author = {Parvez Ahmad},
title = {{HDL Analyzer and Netlist Architect (HANA)}},
note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
}
@misc{MVSIS,
author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
title = {{MVSIS: Logic Synthesis and Verification}},
note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
}
@misc{VIS,
author = {{The VIS group}},
title = {{VIS: A system for Verification and Synthesis}},
note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
}
@misc{ABC,
author = {{Berkeley Logic Synthesis and Verification Group}},
title = {{ABC: A System for Sequential Synthesis and Verification}},
note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
}
@misc{AIGER,
author = {{Armin Biere, Johannes Kepler University Linz, Austria}},
title = {{AIGER}},
note = {\url{http://fmv.jku.at/aiger/}}
}
@misc{XilinxWebPACK,
author = {{Xilinx, Inc.}},
title = {{ISE WebPACK Design Software}},
note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
}
@misc{QuartusWeb,
author = {{Altera, Inc.}},
title = {{Quartus II Web Edition Software}},
note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
}
@misc{OR1200,
title = {{OpenRISC 1200 CPU}},
note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
}
@misc{openMSP430,
title = {{openMSP430 CPU}},
note = {\url{http://opencores.org/project,openmsp430}}
}
@misc{i2cmaster,
title = {{OpenCores I$^2$C Core}},
note = {\url{http://opencores.org/project,i2c}}
}
@misc{k68,
title = {{OpenCores k68 Core}},
note = {\url{http://opencores.org/project,k68}}
}
@misc{bison,
title = {{GNU Bison}},
note = {\url{http://www.gnu.org/software/bison/}}
}
@misc{flex,
title = {{Flex}},
note = {\url{http://flex.sourceforge.net/}}
}
@misc{C_to_Verilog,
title = {{C-to-Verilog}},
note = {\url{http://www.c-to-verilog.com/}}
}
@misc{LegUp,
title = {{LegUp}},
note = {\url{http://legup.eecg.utoronto.ca/}}
}
@misc{LibertyFormat,
title = {{The Liberty Library Modeling Standard}},
note = {\url{http://www.opensourceliberty.org/}}
}
@misc{ASIC-WORLD,
title = {{World of ASIC}},
note = {\url{http://www.asic-world.com/}}
}
@misc{Formality,
title = {{Synopsys Formality Equivalence Checking}},
note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
}
@misc{bigint,
author = {Matt McCutchen},
title = {{C++ Big Integer Library}},
note = {\url{http://mattmccutchen.net/bigint/}}
}
|
