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#include "kernel/yosys.h"
#include "kernel/sigtools.h"

USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN

struct MyPass : public Pass {
    MyPass() : Pass("my_cmd", "just a simple test") { }
    void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
    {
        log("Arguments to my_cmd:\n");
        for (auto &arg : args)
            log("  %s\n", arg.c_str());

        log("Modules in current design:\n");
        for (auto mod : design->modules())
            log("  %s (%zd wires, %zd cells)\n", log_id(mod),
                    GetSize(mod->wires()), GetSize(mod->cells()));
    }
} MyPass;


struct Test1Pass : public Pass {
    Test1Pass() : Pass("test1", "creating the absval module") { }
    void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
    {
        if (design->has("\\absval") != 0)
            log_error("A module with the name absval already exists!\n");

        RTLIL::Module *module = design->addModule("\\absval");
        log("Name of this module: %s\n", log_id(module));

        RTLIL::Wire *a = module->addWire("\\a", 4);
        a->port_input = true;
        a->port_id = 1;

        RTLIL::Wire *y = module->addWire("\\y", 4);
        y->port_output = true;
        y->port_id = 2;

        RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
        module->addNeg(NEW_ID, a, a_inv, true);
        module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);

	module->fixup_ports();
    }
} Test1Pass;


struct Test2Pass : public Pass {
    Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
    void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
    {
        if (design->selection_stack.back().empty())
            log_cmd_error("This command can't operator on an empty selection!\n");

        RTLIL::Module *module = design->modules_.at("\\test");

        RTLIL::SigSpec a(module->wire("\\a")), x(module->wire("\\x")), y(module->wire("\\y"));
        log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"

        SigMap sigmap(module);
        log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
                          sigmap(y) == sigmap(a)); // will print "1 1 1"

        log("Mapped signal x: %s\n", log_signal(sigmap(x)));

        log_header(design, "Doing important stuff!\n");
        log_push();
        for (int i = 0; i < 10; i++)
            log("Log message #%d.\n", i);
        log_pop();
    }
} Test2Pass;

PRIVATE_NAMESPACE_END
an>(['', ' real', ' integer']), i, random_expression())) for i in range(30, 60): if idx < 10: print('localparam p%02d = %s;' % (i, random_expression(maxparam = 30))) else: print('localparam%s p%02d = %s;' % (random.choice(['', ' real', ' integer']), i, random_expression(maxparam = 30))) for i in range(100): print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60))) print('endmodule') with open('temp/uut_%05d.ys' % idx, 'w') as f: with redirect_stdout(f): print('read_verilog uut_%05d.v' % idx) print('rename uut_%05d uut_%05d_syn' % (idx, idx)) print('write_verilog uut_%05d_syn.v' % idx) with open('temp/uut_%05d_tb.v' % idx, 'w') as f: with redirect_stdout(f): print('module uut_%05d_tb;\n' % idx) print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)]))) print('wire [63:0] %s;' % (', '.join(['s%02d' % i for i in range(100)]))) print('uut_%05d ref(%s);' % (idx, ', '.join(['r%02d' % i for i in range(100)]))) print('uut_%05d_syn syn(%s);' % (idx, ', '.join(['s%02d' % i for i in range(100)]))) print('task compare_ref_syn;') print(' input [7:0] i;') print(' input [63:0] r, s;') print(' reg [64*8-1:0] buffer;') print(' integer j;') print(' begin') print(' if (-1 <= $signed(r-s) && $signed(r-s) <= +1) begin') print(' // $display("%d: %b %b", i, r, s);') print(' end else if (r === s) begin ') print(' // $display("%d: %b %b", i, r, s);') print(' end else begin ') print(' for (j = 0; j < 64; j = j+1)') print(' buffer[j*8 +: 8] = r[j] !== s[j] ? "^" : " ";') print(' $display("\\n%3d: %b %b", i, r, s);') print(' $display(" %s %s", buffer, buffer);') print(' end') print(' end') print('endtask') print('initial begin #1;') for i in range(100): print(' compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i)) print('end') print('endmodule')