# read test design read_verilog ../PRESENTATION_ExSyn/techmap_01.v hierarchy -top test # create two version of the design: test_orig and test_mapped copy test test_orig rename test test_mapped # apply the techmap only to test_mapped techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped # create a miter circuit to test equivialence miter -equiv -make_assert -make_outputs test_orig test_mapped miter flatten miter # run equivialence check sat -verify -prove-asserts -show-inputs -show-outputs miter /yosys Git repository'/>

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module NOT(A, Y);
input A;
output Y = ~A;
endmodule

module NAND(A, B, Y);
input A, B;
output Y = ~(A & B);
endmodule

module NOR(A, B, Y);
input A, B;
output Y = ~(A | B);
endmodule

module DFF(C, D, Q);
input C, D;
output reg Q;
always @(posedge C)
	Q <= D;
endmodule