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manual
/
PRESENTATION_ExSyn
/
opt_02.v
blob: 762fc1a89931d644535a2bc801c67d96f96a5caa (
plain
)
1
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module
test
(
input
A
,
output
Y
,
Z
);
assign
Y
=
A
==
A
,
Z
=
A
!=
A
;
endmodule
