// test taken from aes_core from iwls2005 module aes_key_expand_128(clk, kld, key, wo_0, wo_1, wo_2, wo_3); input clk, kld; input [15:0] key; output [3:0] wo_0, wo_1, wo_2, wo_3; reg [3:0] w[3:0]; assign wo_0 = w[0]; assign wo_1 = w[1]; assign wo_2 = w[2]; assign wo_3 = w[3]; always @(posedge clk) begin w[0] <= kld ? key[15:12] : w[0]; w[1] <= kld ? key[11: 8] : w[0]^w[1]; w[2] <= kld ? key[ 7: 4] : w[0]^w[1]^w[2]; w[3] <= kld ? key[ 3: 0] : w[0]^w[1]^w[2]^w[3]; end endmodule 0/yosys' title='iCE40/yosys Git repository'/>
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path: root/manual/PRESENTATION_ExAdv/Makefile
blob: 993a9d9e10c113c594c07fd4414e5b4f03aed871 (plain) 
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all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
		macc_simple_xmap.pdf macc_xilinx_xmap.pdf

select.pdf: select.v select.ys
	../../yosys select.ys

red_or3x1.pdf: red_or3x1_*
	../../yosys red_or3x1_test.ys

sym_mul.pdf: sym_mul_*
	../../yosys sym_mul_test.ys

mymul.pdf: mymul_*
	../../yosys mymul_test.ys

mulshift.pdf: mulshift_*
	../../yosys mulshift_test.ys

addshift.pdf: addshift_*
	../../yosys addshift_test.ys

macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
	../../yosys macc_simple_test.ys

macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
	../../yosys macc_xilinx_test.ys
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