<html><head><title>/xen/arch/ia64/linux-xen/</title></head>
<body>
<h2>/xen/arch/ia64/linux-xen/</h2>
<ul>
<li><a href='/cgit/xen/xen/plain/xen/arch/ia64/?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>../</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/README.origin?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>README.origin</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/efi.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>efi.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/entry.S?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>entry.S</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/entry.h?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>entry.h</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/head.S?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>head.S</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/hpsim_ssc.h?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>hpsim_ssc.h</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/irq_ia64.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>irq_ia64.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/minstate.h?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>minstate.h</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/mm_contig.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>mm_contig.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/pal.S?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>pal.S</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/sal.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>sal.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/setup.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>setup.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/smp.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>smp.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/smpboot.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>smpboot.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/sort.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>sort.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/time.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>time.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/tlb.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>tlb.c</a></li>
  <li><a href='/cgit/xen/xen/plain/xen/arch/ia64/linux-xen/unaligned.c?h=4.1.1-rc2&amp;id=d9cf42324419ac188fdeaa03c799c482120a5da9'>unaligned.c</a></li>
 </ul>
</body></html>
/a>/<a href='/cgit.cgi/iCE40/yosys/tree/manual/APPNOTE_010_Verilog_to_BLIF.tex?id=4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea'>APPNOTE_010_Verilog_to_BLIF.tex</a></div><div class='content'>blob: 0ecdf61942245810f0663fc674da99ad96e44713 (<a href='/cgit.cgi/iCE40/yosys/plain/manual/APPNOTE_010_Verilog_to_BLIF.tex?id=4b9eefe3b6fce79fc0b31a97efde3b5f1ba49cea'>plain</a>)
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<span class="k">\begin</span><span class="nb">{</span>document<span class="nb">}</span>

<span class="k">\title</span><span class="nb">{</span>Yosys Application Note 010: <span class="k">\\</span> Converting Verilog to BLIF<span class="nb">}</span>
<span class="k">\author</span><span class="nb">{</span>Clifford Wolf <span class="k">\\</span> November 2013<span class="nb">}</span>
<span class="k">\maketitle</span>

<span class="k">\begin</span><span class="nb">{</span>abstract<span class="nb">}</span>
Verilog-2005 is a powerful Hardware Description Language (HDL) that can be used
to easily create complex designs from small HDL code. It is the preferred
method of design entry for many designers<span class="k">\footnote</span><span class="nb">{</span>The other half prefers VHDL,
a very different but -- of course -- equally powerful language.<span class="nb">}</span>.

The Berkeley Logic Interchange Format (BLIF) <span class="k">\cite</span><span class="nb">{</span>blif<span class="nb">}</span> is a simple file format for
exchanging sequential logic between programs. It is easy to generate and
easy to parse and is therefore the preferred method of design entry for
many authors of logic synthesis tools.

Yosys <span class="k">\cite</span><span class="nb">{</span>yosys<span class="nb">}</span> is a feature-rich
Open-Source Verilog synthesis tool that can be used to bridge the gap between
the two file formats. It implements most of Verilog-2005 and thus can be used
to import modern behavioral Verilog designs into BLIF-based design flows
without dependencies on proprietary synthesis tools.

The scope of Yosys goes of course far beyond Verilog logic synthesis. But
it is a useful and important feature and this Application Note will focus
on this aspect of Yosys.
<span class="k">\end</span><span class="nb">{</span>abstract<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Installation<span class="nb">}</span>

Yosys written in C++ (using features from C++11) and is tested on modern Linux.
It should compile fine on most UNIX systems with a C++11 compiler. The README
file contains useful information on building Yosys and its prerequisites.

Yosys is a large and feature-rich program with a couple of dependencies. It is,
however, possible to deactivate some of the dependencies in the Makefile,
resulting in features in Yosys becoming unavailable. When problems with building
Yosys are encountered, a user who is only interested in the features of Yosys
that are discussed in this Application Note may deactivate <span class="nb">{</span><span class="k">\tt</span> TCL<span class="nb">}</span>, <span class="nb">{</span><span class="k">\tt</span> Qt<span class="nb">}</span>
and <span class="nb">{</span><span class="k">\tt</span> MiniSAT<span class="nb">}</span> support in the <span class="nb">{</span><span class="k">\tt</span> Makefile<span class="nb">}</span> and may opt against building
<span class="nb">{</span><span class="k">\tt</span> yosys-abc<span class="nb">}</span>.

<span class="k">\bigskip</span>

This Application Note is based on GIT Rev. <span class="nb">{</span><span class="k">\tt</span> e216e0e<span class="nb">}</span> from 2013-11-23 of
Yosys <span class="k">\cite</span><span class="nb">{</span>yosys<span class="nb">}</span>. The Verilog sources used for the examples are taken from
yosys-bigsim <span class="k">\cite</span><span class="nb">{</span>bigsim<span class="nb">}</span>, a collection of real-world designs used for
regression testing Yosys.

<span class="k">\section</span><span class="nb">{</span>Getting Started<span class="nb">}</span>

We start our tour with the Navr<span class="k">\&#39;</span>e processor from yosys-bigsim. The Navr<span class="k">\&#39;</span>e
processor <span class="k">\cite</span><span class="nb">{</span>navre<span class="nb">}</span> is an Open Source AVR clone. It is a single module (<span class="nb">{</span><span class="k">\tt</span>
softusb<span class="k">\_</span>navre<span class="nb">}</span>) in a single design file (<span class="nb">{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre.v<span class="nb">}</span>). It also is
using only features that map nicely to the BLIF format, for example it only
uses synchronous resets.

Converting <span class="nb">{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre.v<span class="nb">}</span> to <span class="nb">{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre.blif<span class="nb">}</span> could not be
easier:

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[H]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=sh]
yosys -o softusb<span class="nb">_</span>navre.blif -S softusb<span class="nb">_</span>navre.v
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
 <span class="k">\renewcommand</span><span class="nb">{</span><span class="k">\figurename</span><span class="nb">}{</span>Listing<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Calling Yosys without script file<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

Behind the scenes Yosys is controlled by synthesis scripts that execute
commands that operate on Yosys&#39; internal state. For example, the <span class="nb">{</span><span class="k">\tt</span> -o
softusb<span class="k">\_</span>navre.blif<span class="nb">}</span> option just adds the command <span class="nb">{</span><span class="k">\tt</span> write<span class="k">\_</span>blif
softusb<span class="k">\_</span>navre.blif<span class="nb">}</span> to the end of the script. Likewise a file on the
command line -- <span class="nb">{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre.v<span class="nb">}</span> in this case -- adds the command
<span class="nb">{</span><span class="k">\tt</span> read<span class="k">\_</span>verilog softusb<span class="k">\_</span>navre.v<span class="nb">}</span> to the beginning of the
synthesis script. In both cases the file type is detected from the
file extension.

Finally the option <span class="nb">{</span><span class="k">\tt</span> -S<span class="nb">}</span> instantiates a built-in default synthesis script.
Instead of using <span class="nb">{</span><span class="k">\tt</span> -S<span class="nb">}</span> one could also specify the synthesis commands
for the script on the command line using the <span class="nb">{</span><span class="k">\tt</span> -p<span class="nb">}</span> option, either using
individual options for each command or by passing one big command string
with a semicolon-separated list of commands. But in most cases it is more
convenient to use an actual script file.

<span class="k">\section</span><span class="nb">{</span>Using a Synthesis Script<span class="nb">}</span>

With a script file we have better control over Yosys. The following script
file replicates what the command from the last section did:

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[H]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=sh]
read<span class="nb">_</span>verilog softusb<span class="nb">_</span>navre.v
hierarchy
proc; opt; memory; opt; techmap; opt
write<span class="nb">_</span>blif softusb<span class="nb">_</span>navre.blif
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
 <span class="k">\renewcommand</span><span class="nb">{</span><span class="k">\figurename</span><span class="nb">}{</span>Listing<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

The first and last line obviously read the Verilog file and write the BLIF
file.

<span class="k">\medskip</span>

The 2nd line checks the design hierarchy and instantiates parametrized
versions of the modules in the design, if necessary. In the case of this
simple design this is a no-op. However, as a general rule a synthesis script
should always contain this command as first command after reading the input
files.

<span class="k">\medskip</span>

The 3rd line does most of the actual work:

<span class="k">\begin</span><span class="nb">{</span>itemize<span class="nb">}</span>
<span class="k">\item</span> The command <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span> is the Yosys&#39; built-in optimizer. It can perform
some simple optimizations such as const-folding and removing unconnected parts
of the design. It is common practice to call opt after each major step in the
synthesis procedure. In cases where too much optimization is not appreciated
(for example when analyzing a design), it is recommended to call <span class="nb">{</span><span class="k">\tt</span> clean<span class="nb">}</span>
instead of <span class="nb">{</span><span class="k">\tt</span> opt<span class="nb">}</span>.
<span class="k">\item</span> The command <span class="nb">{</span><span class="k">\tt</span> proc<span class="nb">}</span> converts <span class="nb">{</span><span class="k">\it</span> processes<span class="nb">}</span> (Yosys&#39; internal
representation of Verilog <span class="nb">{</span><span class="k">\tt</span> always<span class="nb">}</span>- and <span class="nb">{</span><span class="k">\tt</span> initial<span class="nb">}</span>-blocks) to circuits
of multiplexers and storage elements (various types of flip-flops).
<span class="k">\item</span> The command <span class="nb">{</span><span class="k">\tt</span> memory<span class="nb">}</span> converts Yosys&#39; internal representations of
arrays and array accesses to multi-port block memories, and then maps this
block memories to address decoders and flip-flops, unless the option <span class="nb">{</span><span class="k">\tt</span> -nomap<span class="nb">}</span>
is used, in which case the multi-port block memories stay in the design
and can then be mapped to architecture-specific memory primitives using
other commands.
<span class="k">\item</span> The command <span class="nb">{</span><span class="k">\tt</span> techmap<span class="nb">}</span> turns a high-level circuit with coarse grain
cells such as wide adders and multipliers to a fine-grain circuit of simple
logic primitives and single-bit storage elements. The command does that by
substituting the complex cells by circuits of simpler cells. It is possible
to provide a custom set of rules for this process in the form of a Verilog
source file, as we will see in the next section.
<span class="k">\end</span><span class="nb">{</span>itemize<span class="nb">}</span>

Now Yosys can be run with the filename of the synthesis script as argument:

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[H]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=sh]
yosys softusb<span class="nb">_</span>navre.ys
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
 <span class="k">\renewcommand</span><span class="nb">{</span><span class="k">\figurename</span><span class="nb">}{</span>Listing<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Calling Yosys with script file<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\medskip</span>

Now that we are using a synthesis script we can easily modify how Yosys
synthesizes the design. The first thing we should customize is the
call to the <span class="nb">{</span><span class="k">\tt</span> hierarchy<span class="nb">}</span> command:

Whenever it is known that there are no implicit blackboxes in the design, i.e.
modules that are referenced but are not defined, the <span class="nb">{</span><span class="k">\tt</span> hierarchy<span class="nb">}</span> command
should be called with the <span class="nb">{</span><span class="k">\tt</span> -check<span class="nb">}</span> option. This will then cause synthesis
to fail when implicit blackboxes are found in the design.

The 2nd thing we can improve regarding the <span class="nb">{</span><span class="k">\tt</span> hierarchy<span class="nb">}</span> command is that we
can tell it the name of the top level module of the design hierarchy. It will
then automatically remove all modules that are not referenced from this top
level module.

<span class="k">\medskip</span>

For many designs it is also desired to optimize the encodings for the finite
state machines (FSMs) in the design. The <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span> command finds FSMs, extracts
them, performs some basic optimizations and then generate a circuit from
the extracted and optimized description. It would also be possible to tell
the <span class="nb">{</span><span class="k">\tt</span> fsm<span class="nb">}</span> command to leave the FSMs in their extracted form, so they can be
further processed using custom commands. But in this case we don&#39;t want that.

<span class="k">\medskip</span>

So now we have the final synthesis script for generating a BLIF file
for the Navr<span class="k">\&#39;</span>e CPU:

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[H]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=sh]
read<span class="nb">_</span>verilog softusb<span class="nb">_</span>navre.v
hierarchy -check -top softusb<span class="nb">_</span>navre
proc; opt; memory; opt; fsm; opt; techmap; opt
write<span class="nb">_</span>blif softusb<span class="nb">_</span>navre.blif
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
 <span class="k">\renewcommand</span><span class="nb">{</span><span class="k">\figurename</span><span class="nb">}{</span>Listing<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{{</span><span class="k">\tt</span> softusb<span class="k">\_</span>navre.ys<span class="nb">}</span> (improved)<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\section</span><span class="nb">{</span>Advanced Example: The Amber23 ARMv2a CPU<span class="nb">}</span>

Our 2nd example is the Amber23 <span class="k">\cite</span><span class="nb">{</span>amber<span class="nb">}</span>
ARMv2a CPU. Once again we base our example on the Verilog code that is included
in yosys-bigsim <span class="k">\cite</span><span class="nb">{</span>bigsim<span class="nb">}</span>.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[b!]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=sh]
read<span class="nb">_</span>verilog a23<span class="nb">_</span>alu.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>barrel<span class="nb">_</span>shift<span class="nb">_</span>fpga.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>barrel<span class="nb">_</span>shift.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>cache.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>coprocessor.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>core.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>decode.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>execute.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>fetch.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>multiply.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>ram<span class="nb">_</span>register<span class="nb">_</span>bank.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>register<span class="nb">_</span>bank.v
read<span class="nb">_</span>verilog a23<span class="nb">_</span>wishbone.v
read<span class="nb">_</span>verilog generic<span class="nb">_</span>sram<span class="nb">_</span>byte<span class="nb">_</span>en.v
read<span class="nb">_</span>verilog generic<span class="nb">_</span>sram<span class="nb">_</span>line<span class="nb">_</span>en.v
hierarchy -check -top a23<span class="nb">_</span>core
add -global<span class="nb">_</span>input globrst 1
proc -global<span class="nb">_</span>arst globrst
techmap -map adff2dff.v
opt; memory; opt; fsm; opt; techmap
write<span class="nb">_</span>blif amber23.blif
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
 <span class="k">\renewcommand</span><span class="nb">{</span><span class="k">\figurename</span><span class="nb">}{</span>Listing<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span><span class="k">\tt</span> amber23.ys<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>aber23.ys<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

The problem with this core is that it contains no dedicated reset logic.
Instead the coding techniques shown in Listing~<span class="k">\ref</span><span class="nb">{</span>glob<span class="nb">_</span>arst<span class="nb">}</span> are used to
define reset values for the global asynchronous reset in an FPGA
implementation. This design can not be expressed in BLIF as it is. Instead we
need to use a synthesis script that transforms this form to synchronous resets that
can be expressed in BLIF.

(Note that there is no problem if this coding techniques are used to model
ROM, where the register is initialized using this syntax but is never updated
otherwise.)

<span class="k">\medskip</span>

Listing~<span class="k">\ref</span><span class="nb">{</span>aber23.ys<span class="nb">}</span> shows the synthesis script for the Amber23 core. In
line 17 the <span class="nb">{</span><span class="k">\tt</span> add<span class="nb">}</span> command is used to add a 1-bit wide global input signal
with the name <span class="nb">{</span><span class="k">\tt</span> globrst<span class="nb">}</span>. That means that an input with that name is added
to each module in the design hierarchy and then all module instantiations are
altered so that this new signal is connected throughout the whole design
hierarchy.

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[t!]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=Verilog]
reg [7:0] a = 13, b;
initial b = 37;
<span class="k">\end</span><span class="nb">{</span>lstlisting<span class="nb">}</span>
 <span class="k">\renewcommand</span><span class="nb">{</span><span class="k">\figurename</span><span class="nb">}{</span>Listing<span class="nb">}</span>
<span class="k">\caption</span><span class="nb">{</span>Implicit coding of global asynchronous resets<span class="nb">}</span>
<span class="k">\label</span><span class="nb">{</span>glob<span class="nb">_</span>arst<span class="nb">}</span>
<span class="k">\end</span><span class="nb">{</span>figure<span class="nb">}</span>

<span class="k">\begin</span><span class="nb">{</span>figure<span class="nb">}</span>[b!]
<span class="k">\begin</span><span class="nb">{</span>lstlisting<span class="nb">}</span>[language=Verilog]
(* techmap<span class="nb">_</span>celltype = &quot;<span class="s">$</span><span class="nb">adff&quot; </span><span class="o">*)</span><span class="nb"></span>
<span class="nb">module adff</span><span class="m">2</span><span class="nb">dff </span><span class="o">(</span><span class="nb">CLK, ARST, D, Q</span><span class="o">)</span><span class="nb">;</span>

<span class="nb">parameter WIDTH </span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">parameter CLK_POLARITY </span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">parameter ARST_POLARITY </span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb">;</span>
<span class="nb">parameter ARST_VALUE </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">;</span>

<span class="nb">input CLK, ARST;</span>
<span class="nb">input </span><span class="o">[</span><span class="nb">WIDTH</span><span class="o">-</span><span class="m">1</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> D;</span>
<span class="nb">output reg </span><span class="o">[</span><span class="nb">WIDTH</span><span class="o">-</span><span class="m">1</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> Q;</span>

<span class="nb">wire </span><span class="o">[</span><span class="m">1023</span><span class="nb">:</span><span class="m">0</span><span class="o">]</span><span class="nb"> _TECHMAP_DO_ </span><span class="o">=</span><span class="nb"> &quot;proc&quot;;</span>

<span class="nb">wire _TECHMAP_FAIL_ </span><span class="o">=</span><span class="nb"></span>
<span class="nb">    </span><span class="o">!</span><span class="nb">CLK_POLARITY || </span><span class="o">!</span><span class="nb">ARST_POLARITY;</span>

<span class="nb">always @</span><span class="o">(</span><span class="nb">posedge CLK</span><span class="o">)</span><span class="nb"></span>
<span class="nb">        if </span><span class="o">(</span><span class="nb">ARST</span><span class="o">)</span><span class="nb"></span>
<span class="nb">                Q &lt;</span><span class="o">=</span><span class="nb"> ARST_VALUE;</span>
<span class="nb">        else</span>
<span class="nb">                Q &lt;</span><span class="o">=</span><span class="nb"> D;</span>

<span class="nb">endmodule</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\renewcommand</span><span class="nb">{</span><span class="nv">\figurename</span><span class="nb">}{Listing}</span>
<span class="nv">\caption</span><span class="nb">{</span><span class="nv">\tt</span><span class="nb"> adff</span><span class="m">2</span><span class="nb">dff.v}</span>
<span class="nv">\label</span><span class="nb">{adff</span><span class="m">2</span><span class="nb">dff.v}</span>
<span class="nv">\end</span><span class="nb">{figure}</span>

<span class="nb">In line </span><span class="m">18</span><span class="nb"> the {</span><span class="nv">\tt</span><span class="nb"> proc} command is called. But in this script the signal name</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> globrst} is passed to the command as a global reset signal for resetting</span>
<span class="nb">the registers to their assigned initial values.</span>

<span class="nb">Finally in line </span><span class="m">19</span><span class="nb"> the {</span><span class="nv">\tt</span><span class="nb"> techmap} command is used to replace all instances</span>
<span class="nb">of flip</span><span class="o">-</span><span class="nb">flops with asynchronous resets with flip</span><span class="o">-</span><span class="nb">flops with synchronous resets.</span>
<span class="nb">The map file used for this is shown in Listing~</span><span class="nv">\ref</span><span class="nb">{adff</span><span class="m">2</span><span class="nb">dff.v}. Note how the</span>
<span class="nb">{</span><span class="nv">\tt</span><span class="nb"> techmap</span><span class="nv">\_</span><span class="nb">celltype} attribute is used in line </span><span class="m">1</span><span class="nb"> to tell the techmap command</span>
<span class="nb">which cells to replace in the design, how the {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">FAIL</span><span class="nv">\_</span><span class="nb">} wire in</span>
<span class="nb">lines </span><span class="m">15</span><span class="nb"> and </span><span class="m">16</span><span class="nb"> </span><span class="o">(</span><span class="nb">which evaluates to a constant value</span><span class="o">)</span><span class="nb"> determines if the</span>
<span class="nb">parameter set is compatible with this replacement circuit, and how the {</span><span class="nv">\tt</span><span class="nb"></span>
<span class="nv">\_</span><span class="nb">TECHMAP</span><span class="nv">\_</span><span class="nb">DO</span><span class="nv">\_</span><span class="nb">} wire in line </span><span class="m">13</span><span class="nb"> provides a mini synthesis</span><span class="o">-</span><span class="nb">script to be used to</span>
<span class="nb">process this cell.</span>

<span class="nv">\begin</span><span class="nb">{figure</span><span class="o">*</span><span class="nb">}</span>
<span class="nv">\begin</span><span class="nb">{lstlisting}</span><span class="o">[</span><span class="nb">language</span><span class="o">=</span><span class="nb">C</span><span class="o">]</span><span class="nb"></span>
<span class="nb">#include &lt;stdint.h&gt;</span>
<span class="nb">#include &lt;stdbool.h&gt;</span>

<span class="nb">#define BITMAP_SIZE </span><span class="m">64</span><span class="nb"></span>
<span class="nb">#define OUTPORT </span><span class="m">0</span><span class="nb">x</span><span class="m">10000000</span><span class="nb"></span>

<span class="nb">static uint</span><span class="m">32</span><span class="nb">_t bitmap</span><span class="o">[</span><span class="nb">BITMAP_SIZE</span><span class="o">/</span><span class="m">32</span><span class="o">]</span><span class="nb">;</span>

<span class="nb">static void bitmap_set</span><span class="o">(</span><span class="nb">uint</span><span class="m">32</span><span class="nb">_t idx</span><span class="o">)</span><span class="nb"> { bitmap</span><span class="o">[</span><span class="nb">idx</span><span class="o">/</span><span class="m">32</span><span class="o">]</span><span class="nb"> |</span><span class="o">=</span><span class="nb"> </span><span class="m">1</span><span class="nb"> &lt;&lt; </span><span class="o">(</span><span class="nb">idx </span><span class="c">% 32); }</span>
<span class="nb">static bool bitmap_get</span><span class="o">(</span><span class="nb">uint</span><span class="m">32</span><span class="nb">_t idx</span><span class="o">)</span><span class="nb"> { return </span><span class="o">(</span><span class="nb">bitmap</span><span class="o">[</span><span class="nb">idx</span><span class="o">/</span><span class="m">32</span><span class="o">]</span><span class="nb"> &amp; </span><span class="o">(</span><span class="m">1</span><span class="nb"> &lt;&lt; </span><span class="o">(</span><span class="nb">idx </span><span class="c">% 32))) != 0; }</span>
<span class="nb">static void output</span><span class="o">(</span><span class="nb">uint</span><span class="m">32</span><span class="nb">_t val</span><span class="o">)</span><span class="nb"> { </span><span class="o">*((</span><span class="nb">volatile uint</span><span class="m">32</span><span class="nb">_t</span><span class="o">*)</span><span class="nb">OUTPORT</span><span class="o">)</span><span class="nb"> </span><span class="o">=</span><span class="nb"> val; }</span>

<span class="nb">int main</span><span class="o">()</span><span class="nb"> {</span>
<span class="nb">	uint</span><span class="m">32</span><span class="nb">_t i, j, k;</span>
<span class="nb">	output</span><span class="o">(</span><span class="m">2</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">	for </span><span class="o">(</span><span class="nb">i </span><span class="o">=</span><span class="nb"> </span><span class="m">0</span><span class="nb">; i &lt; BITMAP_SIZE; i</span><span class="o">++)</span><span class="nb"> {</span>
<span class="nb">		if </span><span class="o">(</span><span class="nb">bitmap_get</span><span class="o">(</span><span class="nb">i</span><span class="o">))</span><span class="nb"> continue;</span>
<span class="nb">		output</span><span class="o">(</span><span class="m">3</span><span class="o">+</span><span class="m">2</span><span class="o">*</span><span class="nb">i</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">		for </span><span class="o">(</span><span class="nb">j </span><span class="o">=</span><span class="nb"> </span><span class="m">2</span><span class="o">*(</span><span class="m">3</span><span class="o">+</span><span class="m">2</span><span class="o">*</span><span class="nb">i</span><span class="o">)</span><span class="nb">;; j </span><span class="o">+=</span><span class="nb"> </span><span class="m">3</span><span class="o">+</span><span class="m">2</span><span class="o">*</span><span class="nb">i</span><span class="o">)</span><span class="nb"> {</span>
<span class="nb">			if </span><span class="o">(</span><span class="nb">j</span><span class="c">%2 == 0) continue;</span>
<span class="nb">			k </span><span class="o">=</span><span class="nb"> </span><span class="o">(</span><span class="nb">j</span><span class="o">-</span><span class="m">3</span><span class="o">)/</span><span class="m">2</span><span class="nb">;</span>
<span class="nb">			if </span><span class="o">(</span><span class="nb">k &gt;</span><span class="o">=</span><span class="nb"> BITMAP_SIZE</span><span class="o">)</span><span class="nb"> break;</span>
<span class="nb">			bitmap_set</span><span class="o">(</span><span class="nb">k</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">		}</span>
<span class="nb">	}</span>
<span class="nb">	output</span><span class="o">(</span><span class="m">0</span><span class="o">)</span><span class="nb">;</span>
<span class="nb">	return </span><span class="m">0</span><span class="nb">;</span>
<span class="nb">}</span>
<span class="nv">\end</span><span class="nb">{lstlisting}</span>
<span class="nv">\renewcommand</span><span class="nb">{</span><span class="nv">\figurename</span><span class="nb">}{Listing}</span>
<span class="nv">\caption</span><span class="nb">{Test program for the Amber</span><span class="m">23</span><span class="nb"> CPU </span><span class="o">(</span><span class="nb">Sieve of Eratosthenes</span><span class="o">)</span><span class="nb">. Compiled using</span>
<span class="nb">GCC </span><span class="m">4</span><span class="nb">.</span><span class="m">6</span><span class="nb">.</span><span class="m">3</span><span class="nb"> for ARM with {</span><span class="nv">\tt</span><span class="nb"> </span><span class="o">-</span><span class="nb">Os </span><span class="o">-</span><span class="nb">marm </span><span class="o">-</span><span class="nb">march</span><span class="o">=</span><span class="nb">armv</span><span class="m">2</span><span class="nb">a </span><span class="o">-</span><span class="nb">mno</span><span class="o">-</span><span class="nb">thumb</span><span class="o">-</span><span class="nb">interwork</span>
<span class="o">-</span><span class="nb">ffreestanding}, linked with {</span><span class="nv">\tt</span><span class="nb"> </span><span class="o">-</span><span class="nb">{}</span><span class="o">-</span><span class="nb">fix</span><span class="o">-</span><span class="nb">v</span><span class="m">4</span><span class="nb">bx} set and booted with a custom</span>
<span class="nb">setup routine written in ARM assembler.}</span>
<span class="nv">\label</span><span class="nb">{sieve}</span>
<span class="nv">\end</span><span class="nb">{figure</span><span class="o">*</span><span class="nb">}</span>

<span class="nv">\section</span><span class="nb">{Verification of the Amber</span><span class="m">23</span><span class="nb"> CPU}</span>

<span class="nb">The BLIF file for the Amber</span><span class="m">23</span><span class="nb"> core, generated using Listings~</span><span class="nv">\ref</span><span class="nb">{aber</span><span class="m">23</span><span class="nb">.ys}</span>
<span class="nb">and </span><span class="nv">\ref</span><span class="nb">{adff</span><span class="m">2</span><span class="nb">dff.v} and the version of the Amber</span><span class="m">23</span><span class="nb"> RTL source that is bundled</span>
<span class="nb">with yosys</span><span class="o">-</span><span class="nb">bigsim, was verified using the test</span><span class="o">-</span><span class="nb">bench from yosys</span><span class="o">-</span><span class="nb">bigsim.</span>
<span class="nb">It successfully executed the program shown in Listing~</span><span class="nv">\ref</span><span class="nb">{sieve} in the</span>
<span class="nb">test</span><span class="o">-</span><span class="nb">bench.</span>

<span class="nb">For simulation the BLIF file was converted back to Verilog using ABC</span>
<span class="nv">\cite</span><span class="nb">{ABC}. So this test includes the successful transformation of the BLIF</span>
<span class="nb">file into ABC&#39;s internal format as well.</span>

<span class="nb">The only thing left to write about the simulation itself is that it probably</span>
<span class="nb">was one of the most energy inefficient and time consuming ways of successfully</span>
<span class="nb">calculating the first </span><span class="m">31</span><span class="nb"> primes the author has ever conducted.</span>

<span class="nv">\section</span><span class="nb">{Limitations}</span>

<span class="nb">At the time of this writing Yosys does not support multi</span><span class="o">-</span><span class="nb">dimensional memories,</span>
<span class="nb">does not support writing to individual bits of array elements, does not</span>
<span class="nb">support initialization of arrays with {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">readmemb} and {</span><span class="nv">\tt</span><span class="nb"> </span><span class="nv">\$</span><span class="nb">readmemh},</span>
<span class="nb">and has only limited support for tristate logic, to name just a few</span>
<span class="nb">limitations.</span>

<span class="nb">That being said, Yosys can synthesize an overwhelming majority of real</span><span class="o">-</span><span class="nb">world</span>
<span class="nb">Verilog RTL code. The remaining cases can usually be modified to be compatible</span>
<span class="nb">with Yosys quite easily.</span>

<span class="nb">The various designs in yosys</span><span class="o">-</span><span class="nb">bigsim are a good place to look for examples</span>
<span class="nb">of what is within the capabilities of Yosys.</span>

<span class="nv">\section</span><span class="nb">{Conclusion}</span>

<span class="nb">Yosys is a feature</span><span class="o">-</span><span class="nb">rich Verilog</span><span class="o">-</span><span class="m">2005</span><span class="nb"> synthesis tool. It has many uses, but</span>
<span class="nb">one is to provide an easy gateway from high</span><span class="o">-</span><span class="nb">level Verilog code to low</span><span class="o">-</span><span class="nb">level</span>
<span class="nb">logic circuits.</span>

<span class="nb">The command line option {</span><span class="nv">\tt</span><span class="nb"> </span><span class="o">-</span><span class="nb">S} can be used to quickly synthesize Verilog</span>
<span class="nb">code to BLIF files without a hassle.</span>

<span class="nb">With custom synthesis scripts it becomes possible to easily perform high</span><span class="o">-</span><span class="nb">level</span>
<span class="nb">optimizations, such as re</span><span class="o">-</span><span class="nb">encoding FSMs. In some extreme cases, such as the</span>
<span class="nb">Amber</span><span class="m">23</span><span class="nb"> ARMv</span><span class="m">2</span><span class="nb"> CPU, the more advanced Yosys features can be used to change a</span>
<span class="nb">design to fit a certain need without actually touching the RTL code.</span>

<span class="nv">\begin</span><span class="nb">{thebibliography}{</span><span class="m">9</span><span class="nb">}</span>

<span class="nv">\bibitem</span><span class="nb">{yosys}</span>
<span class="nb">Clifford Wolf. The Yosys Open SYnthesis Suite. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\url</span><span class="nb">{http:</span><span class="o">//</span><span class="nb">www.clifford.at</span><span class="o">/</span><span class="nb">yosys</span><span class="o">/</span><span class="nb">}</span>

<span class="nv">\bibitem</span><span class="nb">{bigsim}</span>
<span class="nb">yosys</span><span class="o">-</span><span class="nb">bigsim, a collection of real</span><span class="o">-</span><span class="nb">world Verilog designs for regression testing purposes. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\url</span><span class="nb">{https:</span><span class="o">//</span><span class="nb">github.com</span><span class="o">/</span><span class="nb">cliffordwolf</span><span class="o">/</span><span class="nb">yosys</span><span class="o">-</span><span class="nb">bigsim}</span>

<span class="nv">\bibitem</span><span class="nb">{navre}</span>
<span class="nb">Sebastien Bourdeauducq. Navr</span><span class="nv">\&#39;</span><span class="nb">e AVR clone </span><span class="o">(</span><span class="m">8</span><span class="o">-</span><span class="nb">bit RISC</span><span class="o">)</span><span class="nb">. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\url</span><span class="nb">{http:</span><span class="o">//</span><span class="nb">opencores.org</span><span class="o">/</span><span class="nb">project,navre}</span>

<span class="nv">\bibitem</span><span class="nb">{amber}</span>
<span class="nb">Conor Santifort. Amber ARM</span><span class="o">-</span><span class="nb">compatible core. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\url</span><span class="nb">{http:</span><span class="o">//</span><span class="nb">opencores.org</span><span class="o">/</span><span class="nb">project,amber}</span>

<span class="nv">\bibitem</span><span class="nb">{ABC}</span>
<span class="nb">Berkeley Logic Synthesis and Verification Group. ABC: A System for Sequential Synthesis and Verification. </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\url</span><span class="nb">{http:</span><span class="o">//</span><span class="nb">www.eecs.berkeley.edu</span><span class="o">/</span><span class="nb">~alanmi</span><span class="o">/</span><span class="nb">abc</span><span class="o">/</span><span class="nb">}</span>

<span class="nv">\bibitem</span><span class="nb">{blif}</span>
<span class="nb">Berkeley Logic Interchange Format </span><span class="o">(</span><span class="nb">BLIF</span><span class="o">)</span><span class="nb"> </span><span class="nv">\\</span><span class="nb"></span>
<span class="nv">\url</span><span class="nb">{http:</span><span class="o">//</span><span class="nb">vlsi.colorado.edu</span><span class="o">/</span><span class="nb">~vis</span><span class="o">/</span><span class="nb">blif.ps}</span>

<span class="nv">\end</span><span class="nb">{thebibliography}</span>


<span class="nv">\end</span><span class="nb">{document}</span>
</pre></div>
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