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/****************************************************************************************[IntMap.h]
Copyright (c) 2011, Niklas Sorensson
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and
associated documentation files (the "Software"), to deal in the Software without restriction,
including without limitation the rights to use, copy, modify, merge, publish, distribute,
sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all copies or
substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT
NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************************************/

#ifndef Minisat_IntMap_h
#define Minisat_IntMap_h

#include "Vec.h"

namespace Minisat {

    template<class T> struct MkIndexDefault {
        typename vec<T>::Size operator()(T t) const { return (typename vec<T>::Size)t; }
    };
    
    template<class K, class V, class MkIndex = MkIndexDefault<K> >
    class IntMap {
        vec<V>   map;
        MkIndex  index;
    public:
        explicit IntMap(MkIndex _index = MkIndex()) : index(_index){}
        
        bool     has       (K k) const { return index(k) < map.size(); }

        const V& operator[](K k) const { assert(has(k)); return map[index(k)]; }
        V&       operator[](K k)       { assert(has(k)); return map[index(k)]; }

        const V* begin  () const { return &map[0]; }
        const V* end    () const { return &map[map.size()]; }
        V*       begin  ()       { return &map[0]; }
        V*       end    ()       { return &map[map.size()]; }

        void     reserve(K key, V pad)       { map.growTo(index(key)+1, pad); }
        void     reserve(K key)              { map.growTo(index(key)+1); }
        void     insert (K key, V val, V pad){ reserve(key, pad); operator[](key) = val; }
        void     insert (K key, V val)       { reserve(key); operator[](key) = val; }

        void     clear  (bool dispose = false) { map.clear(dispose); }
        void     moveTo (IntMap& to)           { map.moveTo(to.map); to.index = index; }
        void     copyTo (IntMap& to) const     { map.copyTo(to.map); to.index = index; }
    };


    template<class K, class MkIndex = MkIndexDefault<K> >
    class IntSet
    {
        IntMap<K, char, MkIndex> in_set;
        vec<K>                   xs;
        
    public:
        // Size operations:
        int      size        (void)      const  { return xs.size(); }
        void     clear       (bool free = false){
            if (free)
                in_set.clear(true); 
            else
                for (int i = 0; i < xs.size(); i++)
                    in_set[xs[i]] = 0;
            xs.clear(free);
        }

        // Allow inspecting the internal vector:
        const vec<K>&
                 toVec       ()          const  { return xs; }
        
        // Vector interface:
        K        operator [] (int index) const  { return xs[index]; }
        
        
        void     insert      (K k) { in_set.reserve(k, 0); if (!in_set[k]) { in_set[k] = 1; xs.push(k); } }
        bool     has         (K k) { in_set.reserve(k, 0); return in_set[k]; }
    };

    #if 0
    template<class K, class V, V nil, class MkIndex = MkIndexDefault<K> >
    class IntMapNil {
        vec<V> map;
        V      nil;

    public:
        IntMap(){}
        
        void     reserve(K);
        V&       find   (K);
        const V& operator[](K k) const;

    };
    #endif

//=================================================================================================
} // namespace Minisat
#endif
pan> = { cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::CI) }; for (int i = 0; i < 3; i++) if (inbit[i].wire == nullptr) { if (inbit[i] == State::S1) count_ones++; else count_zeros++; } else non_const_inputs.append(inbit[i]); if (count_zeros >= 2) replacement_output = State::S0; else if (count_ones >= 2) replacement_output = State::S1; else if (GetSize(non_const_inputs) == 1) replacement_output = non_const_inputs; if (GetSize(replacement_output)) { optimized_co.insert(sigmap(cell->getPort(ID::CO)[0])); auto it = cell->attributes.find(ID(SB_LUT4.name)); if (it != cell->attributes.end()) { module->rename(cell, it->second.decode_string()); decltype(Cell::attributes) new_attr; for (const auto &a : cell->attributes) if (a.first.begins_with("\\SB_LUT4.\\")) new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; else if (a.first == ID::src) new_attr.insert(std::make_pair(a.first, a.second)); else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived)) continue; else if (a.first.begins_with("\\SB_CARRY.\\")) continue; else log_abort(); cell->attributes = std::move(new_attr); } module->connect(cell->getPort(ID::CO)[0], replacement_output); module->design->scratchpad_set_bool("opt.did_something", true); log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = ID($lut); auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3))); cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) }); cell->setPort(ID::Y, cell->getPort(ID::O)); cell->unsetPort(ID::B); cell->unsetPort(ID::CI); cell->unsetPort(ID(I0)); cell->unsetPort(ID(I3)); cell->unsetPort(ID::CO); cell->unsetPort(ID::O); cell->setParam(ID::WIDTH, 4); cell->unsetParam(ID(I3_IS_CI)); } continue; } } for (auto cell : sb_lut_cells) { SigSpec inbits; inbits.append(get_bit_or_zero(cell->getPort(ID(I0)))); inbits.append(get_bit_or_zero(cell->getPort(ID(I1)))); inbits.append(get_bit_or_zero(cell->getPort(ID(I2)))); inbits.append(get_bit_or_zero(cell->getPort(ID(I3)))); sigmap.apply(inbits); if (optimized_co.count(inbits[0])) goto remap_lut; if (optimized_co.count(inbits[1])) goto remap_lut; if (optimized_co.count(inbits[2])) goto remap_lut; if (optimized_co.count(inbits[3])) goto remap_lut; if (!sigmap(inbits).is_fully_const()) continue; remap_lut: module->design->scratchpad_set_bool("opt.did_something", true); log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell)); cell->type = ID($lut); cell->setParam(ID::WIDTH, 4); cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT))); cell->unsetParam(ID(LUT_INIT)); cell->setPort(ID::A, SigSpec({ get_bit_or_zero(cell->getPort(ID(I3))), get_bit_or_zero(cell->getPort(ID(I2))), get_bit_or_zero(cell->getPort(ID(I1))), get_bit_or_zero(cell->getPort(ID(I0))) })); cell->setPort(ID::Y, cell->getPort(ID::O)[0]); cell->unsetPort(ID(I0)); cell->unsetPort(ID(I1)); cell->unsetPort(ID(I2)); cell->unsetPort(ID(I3)); cell->unsetPort(ID::O); cell->check(); simplemap_lut(module, cell); module->remove(cell); } } struct Ice40OptPass : public Pass { Ice40OptPass() : Pass("ice40_opt", "iCE40: perform simple optimizations") { } void help() override { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" ice40_opt [options] [selection]\n"); log("\n"); log("This command executes the following script:\n"); log("\n"); log(" do\n"); log(" <ice40 specific optimizations>\n"); log(" opt_expr -mux_undef -undriven [-full]\n"); log(" opt_merge\n"); log(" opt_dff\n"); log(" opt_clean\n"); log(" while <changed design>\n"); log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) override { string opt_expr_args = "-mux_undef -undriven"; log_header(design, "Executing ICE40_OPT pass (performing simple optimizations).\n"); log_push(); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-full") { opt_expr_args += " -full"; continue; } break; } extra_args(args, argidx, design); while (1) { design->scratchpad_unset("opt.did_something"); log_header(design, "Running ICE40 specific optimizations.\n"); for (auto module : design->selected_modules()) run_ice40_opts(module); Pass::call(design, "opt_expr " + opt_expr_args); Pass::call(design, "opt_merge"); Pass::call(design, "opt_dff"); Pass::call(design, "opt_clean"); if (design->scratchpad_get_bool("opt.did_something") == false) break; log_header(design, "Rerunning OPT passes. (Removed registers in this run.)\n"); } design->optimize(); design->sort(); design->check(); log_header(design, "Finished OPT passes. (There is nothing left to do.)\n"); log_pop(); } } Ice40OptPass; PRIVATE_NAMESPACE_END