library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_op is
    generic (
        NBITS_IN                       : natural := 1;
        NBR_OF_CHROMA_IN               : natural := 1;
        NBR_OF_ROW_IN                  : natural := 1;
        NBR_OF_COL_IN                  : natural := 1;
        NBITS_OUT                      : natural := 2;
        NBR_OF_CHROMA_OUT              : natural := 1;
        NBR_OF_ROW_OUT                 : natural := 1;
        NBR_OF_COL_OUT                 : natural := 1;
        NBR_OF_MATRIX_IN               : natural := 1;
        NBR_OF_MATRIX_OUT              : natural := 1);
    port (
        signal clock, rst             : in  std_logic;
        signal in_data                : in  std_logic_vector(NBR_OF_MATRIX_IN*NBR_OF_COL_IN*NBR_OF_ROW_IN*NBR_OF_CHROMA_IN*NBITS_IN-1 downto 0);
        signal out_data               : out std_logic_vector(NBR_OF_MATRIX_OUT*NBR_OF_COL_OUT*NBR_OF_ROW_OUT*NBR_OF_CHROMA_OUT*NBITS_OUT-1 downto 0));
end entity test_op;

architecture rtl of test_op is

    package local_pixel_pkg is new work.pixel_pkg
      generic map (
            NBITS_IN                       => NBITS_IN,
            NBR_OF_CHROMA_IN               => NBR_OF_CHROMA_IN,
            NBITS_OUT                      => NBITS_OUT,
            NBR_OF_CHRO