A simple example design, based on the Digilent BASYS3 board =========================================================== This example uses Yosys for synthesis and Xilinx Vivado for place&route and bit-stream creation. Running Yosys: yosys run_yosys.ys Running Vivado: vivado -nolog -nojournal -mode batch -source run_vivado.tcl Programming board: vivado -nolog -nojournal -mode batch -source run_prog.tcl All of the above: bash run.sh ' href='ssh://git@git.panaceas.org/git/iCE40/yosys' title='iCE40/yosys Git repository'/>
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path: root/frontends/verilog/Makefile.inc
blob: dbaace5854c9762a5d673274e5a1db2c7b52fa71 (plain) 
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GENFILES += frontends/verilog/verilog_parser.tab.cc
GENFILES += frontends/verilog/verilog_parser.tab.hh
GENFILES += frontends/verilog/verilog_parser.output
GENFILES += frontends/verilog/verilog_lexer.cc

frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
	$(Q) mkdir -p $(dir $@)
	$(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<

frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc

frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
	$(Q) mkdir -p $(dir $@)
	$(P) flex -o frontends/verilog/verilog_lexer.cc $<

OBJS += frontends/verilog/verilog_parser.tab.o
OBJS += frontends/verilog/verilog_lexer.o
OBJS += frontends/verilog/preproc.o
OBJS += frontends/verilog/verilog_frontend.o
OBJS += frontends/verilog/const2ast.o
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