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* | | | | Add broken testcasesEddie Hung2019-02-251-0/+46
* | | | | Revert "tests/simple to also do LUT synth"Eddie Hung2019-02-211-1/+0
* | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-211-4/+2
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| * | | | Revert "Add -B option to autotest.sh to append to backend_opts"Eddie Hung2019-02-211-4/+2
* | | | | tests/simple to also do LUT synthEddie Hung2019-02-211-0/+1
* | | | | Working simple_abc9 testsEddie Hung2019-02-211-2/+2
* | | | | Add abc9.v testcase to simple_abc9Eddie Hung2019-02-211-4/+46
* | | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaigEddie Hung2019-02-211-21/+0
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| * | | | Remove simple_defparam testsEddie Hung2019-02-201-21/+0
* | | | | simple_abc9 tests to now preserve memoriesEddie Hung2019-02-201-1/+1
* | | | | Move tests/techmap/abc9 to simple_abc9Eddie Hung2019-02-204-23/+0
* | | | | Add tests/simple_abc9Eddie Hung2019-02-201-0/+23
* | | | | Add a quick abc9 testEddie Hung2019-02-194-0/+29
* | | | | Merge branch 'master' into xaigEddie Hung2019-02-195-8/+92
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| * | | Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-175-8/+93
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| | * | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
| | * | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-154-7/+92
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* | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
* | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
* | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-063-2/+67
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| * | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
| * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
| * | Extend testcaseEddie Hung2019-02-061-2/+34
| * | Add testcaseEddie Hung2019-02-061-0/+10
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* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
* | Add testsEddie Hung2019-02-0416-8/+109
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* Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
* Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-022-0/+44
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| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-021-0/+18
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-021-0/+5
| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-021-8/+14
| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-022-0/+15
* | cmp2lut: new techmap pass.whitequark2019-01-023-2/+33
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* opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-313-0/+23
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-1/+1
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-163-26/+3
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| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-072-4/+1
| * equiv_opt: new command, for verifying optimization passes.whitequark2018-12-072-23/+3
* | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-072-0/+20
* | Add missing .gitignoreClifford Wolf2018-12-061-0/+8
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* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-058-0/+45
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-1/+1
* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-055-0/+43
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2513-0/+64
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| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-2513-0/+64
* | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-207-2/+420
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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-185-9/+246
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
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