| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Added k68 (m68k compatible cpu) test case from verilator | Clifford Wolf | 2013-03-31 | 3 | -0/+61 | |
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| * | Renamed hansimem.v test case to mem_arst.v | Clifford Wolf | 2013-03-24 | 1 | -1/+0 | |
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| * | Added hansimem testcase (memory with async reset) | Clifford Wolf | 2013-03-24 | 1 | -0/+44 | |
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| * | Set execute bit on tests/openmsp430/run-synth.sh for real | Clifford Wolf | 2013-03-17 | 1 | -0/+0 | |
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| * | set executable flags to run-synth.sh, added .gitignore | Johann Glaser | 2013-03-17 | 1 | -0/+3 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | added ckeck for Icarus Verilog, otherwise the tests are silently stopped | Johann Glaser | 2013-03-17 | 1 | -0/+7 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | added more .gitignore files (make test) | Clifford Wolf | 2013-01-05 | 4 | -0/+7 | |
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| * | initial import | Clifford Wolf | 2013-01-05 | 367 | -0/+28611 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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