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* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
* Merge pull request #1949 from YosysHQ/eddie/select_blackboxEddie Hung2020-04-221-0/+28
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| * tests: update select black/white-box testsEddie Hung2020-04-221-0/+7
| * select: add test for not selecting inside black/white boxesEddie Hung2020-04-161-0/+21
* | Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-221-1/+3
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| * | tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
* | | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-222-5/+22
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| * | | design: add testEddie Hung2020-04-162-5/+22
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* | | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-221-0/+13
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| * | | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-211-0/+13
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* | | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-0/+23
* | | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2113-0/+1224
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| * | | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
| * | | Simplify test case scriptEddie Hung2020-04-201-30/+17
| * | | Remove ununsed filesEddie Hung2020-04-205-83/+0
| * | | Modifications of tests as per Eddie's requestdiego2020-04-2015-78/+1237
| * | | Wrong fixed valuediego2020-04-171-1/+1
| * | | Adding tests for dynamic part select optimisationdiego2020-04-167-0/+161
* | | | tests: remove write_ilangEddie Hung2020-04-202-3/+0
* | | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | | tests: add select -unset testsEddie Hung2020-04-162-0/+20
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* | tests: add design -delete testsEddie Hung2020-04-162-0/+18
* | Merge pull request #1943 from YosysHQ/dave/fix-1919David Shah2020-04-161-0/+18
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| * | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+18
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* / opt_expr: Fix X and CO outputs for $alu identity-mapping rules.Marcelina Kościelnicka2020-04-161-8/+66
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* Merge pull request #1933 from YosysHQ/eddie/zinit_moreEddie Hung2020-04-151-2/+96
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| * tests: zinit for new typesEddie Hung2020-04-141-2/+96
* | Merge pull request #1930 from YosysHQ/claire/fix1876Claire Wolf2020-04-151-0/+60
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| * | tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
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* | synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
* | opt_expr: Add more $alu optimizations.Marcelina Kościelnicka2020-04-141-4/+52
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* dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-141-0/+25
* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-3/+8
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| * support using previously declared types/localparams/params in packageJeff Wang2020-04-071-3/+8
* | zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-131-1/+8
* | zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-131-4/+31
* | tests: zinit on $adffEddie Hung2020-04-131-19/+18
* | Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
* | opt_expr: Optimize multiplications with low 0 bits in operands.Marcelina Kościelnicka2020-04-131-0/+28
* | Add .gitignore to tests/select/Xiretza2020-04-121-0/+1
* | Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
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| * | ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
| * | ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
| * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-5/+305
| * | ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| * | ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-20/+179
| * | ice40: remove impossible test.whitequark2020-02-061-15/+0
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