| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Fix "make vgtest" so it runs to the end (but now it fails ;) | Claire Xenia Wolf | 2021-09-23 | 40 | -79/+79 |
* | | sv: support wand and wor of data types | Zachary Snow | 2021-09-21 | 2 | -0/+39 |
* | | verilog: fix multiple AST_PREFIX scope resolution issues | Zachary Snow | 2021-09-21 | 2 | -0/+100 |
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* | abc9: make re-entrant (#2993) | Eddie Hung | 2021-09-09 | 1 | -0/+20 |
* | abc9: holes module to instantiate cells with NEW_ID (#2992) | Eddie Hung | 2021-09-09 | 1 | -0/+14 |
* | abc9: replace cell type/parameters if derived type already processed (#2991) | Eddie Hung | 2021-09-09 | 1 | -0/+7 |
* | sv: support declaration in generate for initialization | Zachary Snow | 2021-08-31 | 8 | -0/+114 |
* | sv: support declaration in procedural for initialization | Zachary Snow | 2021-08-30 | 4 | -0/+56 |
* | opt_clean: Make the init attribute follow the FF's Q. | Marcelina Kościelnicka | 2021-08-22 | 1 | -2/+2 |
* | Gowin: deal with active-low tristate (#2971) | Pepijn de Vos | 2021-08-20 | 1 | -1/+2 |
* | proc_prune: Make assign removal and promotion per-bit, remember promoted bits. | Marcelina Kościelnicka | 2021-08-14 | 1 | -0/+22 |
* | Add opt_mem_widen pass. | Marcelina Kościelnicka | 2021-08-14 | 1 | -0/+36 |
* | memory_share: Add -nosat and -nowiden options. | Marcelina Kościelnicka | 2021-08-14 | 9 | -1/+228 |
* | memory_dff: Recognize soft transparency logic. | Marcelina Kościelnicka | 2021-08-13 | 3 | -0/+904 |
* | Add new opt_mem_priority pass. | Marcelina Kościelnicka | 2021-08-13 | 1 | -0/+205 |
* | sv: improve support for wire and var with user-defined types | Brett Witherspoon | 2021-08-12 | 2 | -0/+108 |
* | test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer. | Marcelina Kościelnicka | 2021-08-11 | 2 | -78/+156 |
* | memory_dff: Recognize read ports with reset / initial value. | Marcelina Kościelnicka | 2021-08-11 | 3 | -1/+55 |
* | proc_memwr: Use the v2 memwr cell. | Marcelina Kościelnicka | 2021-08-11 | 2 | -5/+5 |
* | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 8 | -32/+32 |
* | opt_merge: Use FfInitVals. | Marcelina Kościelnicka | 2021-08-08 | 2 | -1/+43 |
* | proc_rmdead: use explicit pattern set when there are no wildcards | Zachary Snow | 2021-07-29 | 3 | -0/+323 |
* | genrtlil: add width detection for AST_PREFIX nodes | Zachary Snow | 2021-07-29 | 1 | -0/+18 |
* | opt_lut: Allow more than one -dlogic per cell type. | Marcelina Kościelnicka | 2021-07-29 | 1 | -0/+24 |
* | verilog: save and restore overwritten macro arguments | Zachary Snow | 2021-07-28 | 2 | -0/+23 |
* | verilog: Emit $meminit_v2 cell. | Marcelina Kościelnicka | 2021-07-28 | 1 | -4/+4 |
* | opt_expr: Propagate constants to port connections. | Marcelina Kościelnicka | 2021-07-27 | 2 | -0/+15 |
* | Add support for parsing the SystemVerilog 'bind' construct | Rupert Swarbrick | 2021-07-16 | 14 | -0/+164 |
* | sv: fix two struct access bugs | Zachary Snow | 2021-07-15 | 2 | -0/+92 |
* | Add a test for interfaces on modules loaded on-demand | Rupert Swarbrick | 2021-07-14 | 5 | -2/+48 |
* | sv: fix up end label checking | Zachary Snow | 2021-06-16 | 6 | -0/+80 |
* | Add regression test for #2824. | Marcelina Kościelnicka | 2021-06-11 | 1 | -0/+7 |
* | Merge pull request #2817 from YosysHQ/claire/fixemails | Claire Xen | 2021-06-09 | 7 | -79/+79 |
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| * | More deadname stuff | Claire Xenia Wolf | 2021-06-09 | 2 | -4/+4 |
| * | More deadname stuff | Claire Xenia Wolf | 2021-06-09 | 1 | -1/+1 |
| * | Use HTTPS for website links, gatecat email | Claire Xenia Wolf | 2021-06-09 | 1 | -1/+1 |
| * | Fix files with CRLF line endings | Claire Xenia Wolf | 2021-06-09 | 3 | -73/+73 |
| * | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 1 | -1/+1 |
* | | verilog: check for module scope identifiers during width detection | Zachary Snow | 2021-06-08 | 1 | -0/+11 |
* | | mem2reg: tolerate out of bounds constant accesses | Zachary Snow | 2021-06-08 | 3 | -0/+52 |
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* | sv: support tasks and functions within packages | Zachary Snow | 2021-06-01 | 2 | -0/+34 |
* | memory_map: Improve start_offset handling. | Marcelina Kościelnicka | 2021-05-31 | 1 | -0/+100 |
* | memory_bram: Reuse extract_rdff helper for make_outreg. | Marcelina Kościelnicka | 2021-05-25 | 4 | -17/+14 |
* | verilog: fix case expression sign and width handling | Zachary Snow | 2021-05-25 | 2 | -0/+108 |
* | sv: support remaining assignment operators | Zachary Snow | 2021-05-25 | 1 | -0/+23 |
* | opt_mem_feedback: Respect write port priority. | Marcelina Kościelnicka | 2021-05-25 | 1 | -0/+47 |
* | opt_mem_feedback: Rewrite feedback path finding logic. | Marcelina Kościelnicka | 2021-05-24 | 2 | -0/+243 |
* | Add new helper class for merging FFs into cells, use for memory_dff. | Marcelina Kościelnicka | 2021-05-23 | 1 | -0/+17 |
* | opt_mem: Remove write ports with const-0 EN. | Marcelina Kościelnicka | 2021-05-23 | 1 | -0/+34 |
* | tests/blif: Add missing gitignore | Marcelina Kościelnicka | 2021-05-20 | 1 | -0/+1 |