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* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-058-0/+45
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-1/+1
* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-055-0/+43
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2513-0/+64
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| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-2513-0/+64
* | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-207-2/+420
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* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-185-9/+246
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-152-0/+75
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| * Modified errors into warningsUdi Finkelstein2018-06-051-4/+38
| * reg_wire_error test needs the -sv flag so it is run via a script so it had to...Udi Finkelstein2018-06-052-0/+1
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-0/+40
* | Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
* | autotest.sh: Change from /bin/bash to /usr/bin/env bashJohnny Sorocil2018-05-061-1/+1
* | Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
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* Major redesign of Verific SVA importerClifford Wolf2018-02-271-1/+1
* Add support for SVA throughout via VerificClifford Wolf2018-02-211-1/+1
* Add support for SVA sequence concatenation ranges via verificClifford Wolf2018-02-182-0/+20
* Add support for SVA until statements via VerificClifford Wolf2018-02-181-0/+19
* Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFFClifford Wolf2018-02-151-0/+34
* Remove PSL example from tests/sva/Clifford Wolf2017-10-202-35/+1
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-292-0/+2
* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-5/+11
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-8/+18
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-6/+5
* $size() now works with memories as well!Udi Finkelstein2017-09-261-2/+4
* Add $size() function. At the moment it works only on expressions, not on memo...Udi Finkelstein2017-09-261-0/+15
* Add simple VHDL+PSL exampleClifford Wolf2017-07-284-17/+64
* Improve Verific SVA importerClifford Wolf2017-07-271-7/+8
* Add counter.sv SVA testClifford Wolf2017-07-271-0/+29
* Improve SVA tests, add Makefile and scriptsClifford Wolf2017-07-2711-9/+110
* Add more SVA test cases for future Verific workClifford Wolf2017-07-225-1/+74
* Add some simple SVA test cases for future Verific workClifford Wolf2017-07-224-0/+45
* Squelch trailing whitespaceLarry Doolittle2017-04-121-1/+1
* Fixed typo in tests/simple/arraycells.vClifford Wolf2017-01-041-1/+1
* Build hotfix in tests/unit/MakefileClifford Wolf2016-12-111-1/+1
* Improved unit test structurerodrigosiqueira2016-12-101-11/+18
* Added required structure to implement unit testsrodrigosiqueira2016-12-043-0/+56
* Added support for hierarchical defparamsClifford Wolf2016-11-151-0/+23
* Added support for (single-clock) transparent memories to bram testsClifford Wolf2016-11-012-10/+23
* Fixed "make test" for git head of iverilogClifford Wolf2016-10-111-1/+1
* Merge branch 'master' of https://github.com/brouhaha/yosysClifford Wolf2016-09-2313-16/+161
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| * Add optional SEED=n command line option to Makefile, and -S n command line op...Eric Smith2016-09-2213-16/+161
* | Added autotest.sh -IClifford Wolf2016-09-201-16/+19
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* Fix for modules with big interfaces.Kaj Tuomi2016-09-131-2/+2
* Fixed bug with memories that do not have a down-to-zero data widthClifford Wolf2016-08-221-0/+30
* Added another mem2reg test caseClifford Wolf2016-08-211-0/+11
* Another bugfix in mem2reg codeClifford Wolf2016-08-211-0/+22