| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | verlog: allow shadowing module ports within generate blocks | Zachary Snow | 2021-02-07 | 1 | -0/+12 |
| This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs. | |||||
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index : iCE40/yosys | |
| [no description] |
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