aboutsummaryrefslogtreecommitdiffstats
path: root/tests/verilog/genblk_port_decl.ys
Commit message (Expand)AuthorAgeFilesLines
* verlog: allow shadowing module ports within generate blocksZachary Snow2021-02-071-0/+12
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 22:43:00 +0000