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* Some test related fixesClifford Wolf2015-02-121-1/+1
* Added "synth" commandClifford Wolf2014-09-141-2/+2
* Fixed autotest for non-basename argumentsClifford Wolf2014-09-061-0/+3
* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-301-2/+4
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-031-1/+1
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-011-2/+5
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-301-6/+15
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-291-1/+1
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-211-1/+1
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-171-1/+1
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-161-2/+11
* Progress in Verific bindingsClifford Wolf2014-03-171-1/+9
* Progress in Verific bindingsClifford Wolf2014-03-141-5/+9
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-151-5/+8
* Updated ABC and some related changesClifford Wolf2014-02-131-2/+1
* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-121-1/+2
* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-031-50/+10
* Added autotest.sh -p optionClifford Wolf2014-01-021-3/+8
* Use "abc -dff" in "make test"Clifford Wolf2013-12-311-3/+2
* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-311-1/+1
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-241-1/+1
* Added modelsim support to autotestClifford Wolf2013-11-241-2/+10
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-151-2/+2
* Added $div and $mod technology mappingClifford Wolf2013-08-091-3/+3
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-091-2/+2
* initial importClifford Wolf2013-01-051-0/+164