iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Some test related fixes	Clifford Wolf	2015-02-12	1	-1/+1
*	Added "synth" command	Clifford Wolf	2014-09-14	1	-2/+2
*	Fixed autotest for non-basename arguments	Clifford Wolf	2014-09-06	1	-0/+3
*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30	1	-2/+4
*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03	1	-1/+1
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-2/+5
*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30	1	-6/+15
*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	1	-1/+1
*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21	1	-1/+1
*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17	1	-1/+1
*	Added note to "make test": use git checkout of iverilog	Clifford Wolf	2014-07-16	1	-2/+11
*	Progress in Verific bindings	Clifford Wolf	2014-03-17	1	-1/+9
*	Progress in Verific bindings	Clifford Wolf	2014-03-14	1	-5/+9
*	Added frontend (-f) option to autotest.sh	Clifford Wolf	2014-02-15	1	-5/+8
*	Updated ABC and some related changes	Clifford Wolf	2014-02-13	1	-2/+1
*	Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)	Clifford Wolf	2014-02-12	1	-1/+2
*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03	1	-50/+10
*	Added autotest.sh -p option	Clifford Wolf	2014-01-02	1	-3/+8
*	Use "abc -dff" in "make test"	Clifford Wolf	2013-12-31	1	-3/+2
*	Fixed commented out techmap call in tests/tools/autotest.sh	Clifford Wolf	2013-12-31	1	-1/+1
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	1	-1/+1
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24	1	-2/+10
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	1	-2/+2
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09	1	-3/+3
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-2/+2
*	initial import	Clifford Wolf	2013-01-05	1	-0/+164