Commit message (Expand) | Author | Age | Files | Lines | |
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* | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 | 1 | -1/+1 |
* | Added modelsim support to autotest | Clifford Wolf | 2013-11-24 | 1 | -2/+10 |
* | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 | 1 | -2/+2 |
* | Added $div and $mod technology mapping | Clifford Wolf | 2013-08-09 | 1 | -3/+3 |
* | Major redesign of expr width/sign detecion (verilog/ast frontend) | Clifford Wolf | 2013-07-09 | 1 | -2/+2 |
* | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+164 |