| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | iopadmap: Emit tristate buffers with const OE for some edge cases. | Marcin Kościelnicki | 2019-12-25 | 1 | -0/+23 |
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| * | iopadmap: Refactor and fix tristate buffer mapping. (#1527) | Marcin Kościelnicki | 2019-12-04 | 1 | -0/+99 |
| | | | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not). | ||||
| * | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -5/+16 |
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| * | Merge pull request #1422 from YosysHQ/eddie/aigmap_select | Clifford Wolf | 2019-10-03 | 1 | -0/+10 |
| |\ | | | | | Add -select option to aigmap | ||||
| | * | Add quick test | Eddie Hung | 2019-09-30 | 1 | -0/+10 |
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| * | | Extend test with renaming cells with prefix too | Eddie Hung | 2019-10-02 | 1 | -0/+2 |
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| * | | Add test | Eddie Hung | 2019-09-30 | 1 | -0/+16 |
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| * | Fix _TECHMAP_REMOVEINIT_ handling. | Marcin Kościelnicki | 2019-09-27 | 1 | -2/+12 |
| | | | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396. | ||||
| * | Hell let's add the original #1381 testcase too | Eddie Hung | 2019-09-20 | 1 | -3/+22 |
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| * | Add testcase | Eddie Hung | 2019-09-20 | 1 | -0/+43 |
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| * | Added extractinv pass | Marcin Kościelnicki | 2019-09-19 | 1 | -0/+41 |
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| * | Add -match-init option to dff2dffs. | Marcin Kościelnicki | 2019-09-11 | 1 | -0/+50 |
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| * | techmap: Add support for extracting init values of ports | Marcin Kościelnicki | 2019-09-07 | 1 | -0/+98 |
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| * | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -5/+33 |
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| * | Improve tests to check that clkbuf is connected to expected | Eddie Hung | 2019-08-26 | 1 | -6/+21 |
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| * | Check clkbuf_inhibit=1 is ignored for custom selection | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
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| * | Add simple clkbufmap tests | Eddie Hung | 2019-08-23 | 1 | -0/+52 |
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| * | tests/techmap/run-test.sh to cope with *.ys | Eddie Hung | 2019-08-23 | 2 | -7/+18 |
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| * | Add test | Eddie Hung | 2019-08-20 | 3 | -0/+15 |
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| * | Added read-enable to memory model | Clifford Wolf | 2015-09-25 | 1 | -1/+8 |
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| * | Added $meminit support to "memory" command | Clifford Wolf | 2015-02-14 | 1 | -0/+5 |
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| * | Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface | Clifford Wolf | 2014-07-16 | 1 | -2/+13 |
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| * | Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
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| * | Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog) | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
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| * | Use private namespace in mem_simple_4x1_map | Clifford Wolf | 2014-02-21 | 1 | -4/+4 |
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| * | Added tests/techmap/mem_simple_4x1 | Clifford Wolf | 2014-02-21 | 7 | -0/+214 |
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index : iCE40/yosys | |
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