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* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-2/+13
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* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
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* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
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* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-211-4/+4
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* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-217-0/+214