| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add v2 memory cells. | Marcelina Kościelnicka | 2021-08-11 | 1 | -1/+1 |
| * | ast/simplify: don't bitblast async ROMs declared as `logic`. | whitequark | 2020-05-05 | 1 | -0/+3 |
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index : iCE40/yosys | |
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