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* Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
* fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
* Add missing .gitignoreClifford Wolf2018-12-061-0/+8
* Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-207-2/+420
* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-185-0/+327