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* Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
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* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-2/+5
| | | | test case
* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-181-0/+41