Basic test for checking correct synthesis of SystemVerilog interfaces

1 files changed, 41 insertions, 0 deletions

diff --git a/tests/svinterfaces/runone.sh b/tests/svinterfaces/runone.sh
new file mode 100755
index 000000000..345801389
--- /dev/null
+++ b/tests/svinterfaces/runone.sh
@@ -0,0 +1,41 @@
+#!/bin/bash
+
+
+TESTNAME=$1
+
+STDOUTFILE=${TESTNAME}.log_stdout
+STDERRFILE=${TESTNAME}.log_stderr
+
+echo "" > $STDOUTFILE
+echo "" > $STDERRFILE
+
+echo -n "Test: ${TESTNAME} -> "
+
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}.sv ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_syn.v" >> $STDOUTFILE >> $STDERRFILE
+$PWD/../../yosys -p "read_verilog -sv ${TESTNAME}_ref.v ; hierarchy -check -top TopModule ; synth ; write_verilog ${TESTNAME}_ref_syn.v" >> $STDOUTFILE >> $STDERRFILE
+
+rm -f a.out reference_result.txt dut_result.txt
+
+set -e
+
+iverilog -g2012 ${TESTNAME}_syn.v
+iverilog -g2012 ${TESTNAME}_ref_syn.v
+
+set +e
+
+iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_ref_syn.v
+./a.out
+mv output.txt reference_result.txt
+iverilog -g2012 ${TESTNAME}_tb.v ${TESTNAME}_syn.v
+./a.out
+mv output.txt dut_result.txt
+
+diff reference_result.txt dut_result.txt > ${TESTNAME}.diff
+RET=$?
+if [ "$RET" != "0" ] ; then
+    echo "ERROR!"
+    exit -1
+fi
+
+echo "ok"
+exit 0