| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Bugfix in partsel.v signed indices test cases | Claire Wolf | 2020-05-02 | 1 | -2/+2 |
| * | Add tests based on the test case from #1990 | Claire Wolf | 2020-05-02 | 1 | -0/+46 |
| * | Fix partsel expr bit width handling and add test case | Claire Wolf | 2020-03-08 | 1 | -0/+4 |
| * | Added support for "upto" wires to Verilog front- and back-end | Clifford Wolf | 2014-07-28 | 1 | -0/+57 |
| * | Renamed some of the test cases in tests/simple to avoid name collisions | Clifford Wolf | 2014-07-25 | 1 | -1/+1 |
| * | Implemented indexed part selects | Clifford Wolf | 2013-11-20 | 1 | -0/+5 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |