| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix "make vgtest" so it runs to the end (but now it fails ;) | Claire Xenia Wolf | 2021-09-23 | 1 | -1/+1 |
| * | verilog: fix case expression sign and width handling | Zachary Snow | 2021-05-25 | 1 | -0/+59 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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