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* support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-292-0/+34
* Added yet another resource sharing test caseClifford Wolf2014-07-202-0/+49
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-052-0/+19
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-122-2/+2
* Added test cases for expose -evert-dffClifford Wolf2014-02-082-0/+48
* Added splice commandClifford Wolf2014-02-072-0/+28
* Added counters sat test caseClifford Wolf2014-02-062-0/+45
* Added test cases for sat commandClifford Wolf2014-02-046-0/+126