| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars... | Udi Finkelstein | 2018-10-25 | 1 | -0/+7 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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