index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
tests
/
errors
/
syntax_err07.v
Commit message (
Expand
)
Author
Age
Files
Lines
*
Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...
Udi Finkelstein
2018-10-25
1
-0
/
+6