iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.	Marcelina Kościelnicka	2021-08-11	1	-51/+102
\| \| \| \| \| \| \| \| \| \|	These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
*	Add v2 memory cells.	Marcelina Kościelnicka	2021-08-11	1	-17/+17
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*	tests: remove write_ilang	Eddie Hung	2020-04-20	1	-2/+0
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*	ecp5: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-16/+62
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*	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	1	-0/+284
	This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).